The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An active LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deselected as does the internalPower-on reset function.
標(biāo)簽： channel 9548A 9548 PCA
上傳時間： 2013-10-13
上傳用戶：bakdesec
MSP430系列單片機(jī)C語言程序設(shè)計與開發(fā)MSP430系列是一個具有明顯技術(shù)特色的單片機(jī)品種。關(guān)于它的硬件特性及匯編語言程序設(shè)計已在《MSP430系列超低功耗16位單片機(jī)的原理與應(yīng)用》及《MSP430系列 FLASH型超低功耗16位單片機(jī)》等書中作了全面介紹。《MSP430系列單片機(jī)C語言程序設(shè)計與開發(fā)》介紹IAR公司為MSP430系列單片機(jī)配備的C程序設(shè)計語言C430。書中敘述了C語言的基本概念、C430的擴(kuò)展特性及C庫函數(shù)；對C430的集成開發(fā)環(huán)境的使用及出錯信息作了詳盡的說明；并以MSP430F149為例，對各種應(yīng)用問題及外圍模塊操作提供了典型的C程序例程，供讀者在今后的C430程序設(shè)計中參考。 《MSP430系列單片機(jī)C語言程序設(shè)計與開發(fā)》可以作為高等院校計算機(jī)、自動化及電子技術(shù)類專業(yè)的教學(xué)參考書，也可作為工程技術(shù)人員設(shè)計開發(fā)時的技術(shù)資料。MSP430系列超低功耗16位單片機(jī)的原理與應(yīng)用目錄MSP430系列單片機(jī)C語言程序設(shè)計與開發(fā) 目錄 第1章 C語言基本知識1.1 標(biāo)識符與關(guān)鍵字11.1.1 標(biāo)識符11.1.2 關(guān)鍵字11.2 數(shù)據(jù)基本類型21.2.1 整型數(shù)據(jù)21.2.2 實(shí)型數(shù)據(jù)31.2.3 字符型數(shù)據(jù)41.2.4 各種數(shù)據(jù)轉(zhuǎn)換關(guān)系61.3 C語言的運(yùn)算符71.3.1 算術(shù)運(yùn)算符71.3.2 關(guān)系運(yùn)算符和邏輯運(yùn)算符71.3.3 賦值運(yùn)算符81.3.4 逗號運(yùn)算符81.3.5 ? 與 ：運(yùn)算符81.3.6 強(qiáng)制轉(zhuǎn)換運(yùn)算符91.3.7 各種運(yùn)算符優(yōu)先級列表91.4 程序設(shè)計的三種基本結(jié)構(gòu)101.4.1 語句的概念101.4.2 順序結(jié)構(gòu)111.4.3 選擇結(jié)構(gòu)121.4.4 循環(huán)結(jié)構(gòu)141.5 函數(shù)181.5.1 函數(shù)定義181.5.2 局部變量與全局變量191.5.3 形式參數(shù)與實(shí)際參數(shù)201.5.4 函數(shù)調(diào)用方式201.5.5 函數(shù)嵌套調(diào)用211.5.6 變量的存儲類別221.5.7 內(nèi)部函數(shù)和外部函數(shù)231.6 數(shù)組231.6.1 一維數(shù)組241.6.2 多維數(shù)組241.6.3 字符數(shù)組261.7 指針271.7.1 指針與地址的概念271.7.2 指針變量的定義281.7.3 指針變量的引用281.7.4 數(shù)組的指針281.7.5 函數(shù)的指針301.7.6 指針數(shù)組311.8 結(jié)構(gòu)和聯(lián)合321.8.1 結(jié)構(gòu)定義321.8.2 結(jié)構(gòu)類型變量的定義331.8.3 結(jié)構(gòu)類型變量的初始化341.8.4 結(jié)構(gòu)類型變量的引用341.8.5 聯(lián)合341.9 枚舉361.9.1 枚舉的定義361.9.2 枚舉元素的值371.9. 3 枚舉變量的使用371.10 類型定義381.10.1 類型定義的形式381.10.2 類型定義的使用381.11 位運(yùn)算391.11.1 位運(yùn)算符391.11.2 位域401.12 預(yù)處理功能411.12.1 簡單宏定義和帶參數(shù)宏定義411.12.2 文件包含431.12.3 條件編譯命令44第2章 C430--MSP430系列的C語言2.1 MSP430系列的C語言452.1.1 C430概述452.1.2 C430程序設(shè)計工作流程462.1.3 開始462.1.4 C430程序生成472.2 C430的數(shù)據(jù)表達(dá)482.2.1 數(shù)據(jù)類型482.2.2 編碼效率502.3 C430的配置512.3.1 引言512.3. 2 存儲器分配522.3.3 堆棧體積522.3.4 輸入輸出522.3.5 寄存器的訪問542.3.6 堆體積542.3.7 初始化54第3章 C430的開發(fā)調(diào)試環(huán)境3.1 引言563.1.1 Workbench特性563.1.2 Workbench的內(nèi)嵌編輯器特性563.1.3 C編譯器特性573.1. 4 匯編器特性573.1.5 連接器特性583.1.6 庫管理器特性583.1.7 C?SPY調(diào)試器特性593.2 Workbench概述593.2.1 項(xiàng)目管理模式593.2.2 選項(xiàng)設(shè)置603.2.3 建立項(xiàng)目603.2.4 測試代碼613.2.5 樣本應(yīng)用程序613.3 Workbench的操作623.3.1 開始633.3.2 編譯項(xiàng)目683.3.3 連接項(xiàng)目693.3.4 調(diào)試項(xiàng)目713.3.5 使用Make命令733.4 Workbench的功能匯總753.4.1 Workbench的窗口753.4.2 Workbench的菜單功能813.5 Workbench的內(nèi)嵌編輯器993.5.1 內(nèi)嵌編輯器操作993.5.2 編輯鍵說明993.6 C?SPY概述1013.6.1 C?SPY的C語言級和匯編語言級調(diào)試1013.6.2 程序的執(zhí)行1023.7 C?SPY的操作1033.7.1 程序生成1033.7.2 編譯與連接1033.7.3 C?SPY運(yùn)行1033.7.4 C語言級調(diào)試1043.7.5 匯編級調(diào)試1113.8 C?SPY的功能匯總1133.8.1 C?SPY的窗口1133.8.2 C?SPY的菜單命令功能1203.9 C?SPY的表達(dá)式與宏1323.9.1 匯編語言表達(dá)式1323.9.2 C語言表達(dá)式1333.9.3 C?SPY宏1353.9.4 C?SPY的設(shè)置宏1373.9.5 C?SPY的系統(tǒng)宏137 第4章 C430程序設(shè)計實(shí)例4.1 程序設(shè)計與調(diào)試環(huán)境1434.1.1 程序設(shè)計調(diào)試集成環(huán)境1434.1.2 設(shè)備連接1444.1.3 ProF149實(shí)驗(yàn)系統(tǒng)1444.2 數(shù)值計算1454.2.1 C語言表達(dá)式1454.2.2 利用MPY實(shí)現(xiàn)運(yùn)算1464.3 循環(huán)結(jié)構(gòu)1474.4 選擇結(jié)構(gòu)1484.5 SFR訪問1494.6 RAM訪問1504.7 FLASH訪問1514.8 WDT操作1534.8. 1 WDT使程序自動復(fù)位1534.8.2 程序?qū)ATCHDOG計數(shù)溢出的控制1544.8.3 WDT的定時器功能1554.9 Timer操作1554.9.1 用Timer產(chǎn)生時鐘信號1554.9.2 用Timer檢測脈沖寬度1564.10 UART操作1574.10.1 點(diǎn)對點(diǎn)通信1574.10.2 點(diǎn)對多點(diǎn)通信1604.11 SPI操作1634.12 比較器操作1654.13 ADC12操作1674.13.1 單通道單次轉(zhuǎn)換1674.13.2 序列通道多次轉(zhuǎn)換1684.14 時鐘模塊操作1704.15 中斷服務(wù)程序1714.16 省電工作模式1754.17 調(diào)用匯編語言子程序1764.17.1 程序舉例1764.17.2 生成C程序調(diào)用的匯編子程序177第5章 C430的擴(kuò)展特性5.1 C430的語言擴(kuò)展概述1785.1.1 擴(kuò)展關(guān)鍵字1785.1.2 #pragma編譯命令1785.1.3 預(yù)定義符號1795.1.4 本征函數(shù)1795.1.5 其他擴(kuò)展特性1795.2 C430的關(guān)鍵字?jǐn)U展1795.2.1 interrupt1805.2.2 monitor1805.2.3 no_init1815.2.4 sfrb1815.2.5 sfrw1825.3 C430的 #pragma編譯命令1825.3.1 bitfields=default1825.3.2 bitfields=reversed1825.3.3 codeseg1835.3.4 function=default1835.3.5 function=interrupt1845.3.6 function=monitor1845.3.7 language=default1845.3.8 language=extended1845.3.9 memory=constseg1855.3.10 memory=dataseg1855.3.11 memory=default1855.3.12 memory=no_init1865.3.13 warnings=default1865.3.14 warnings=off1865.3.15 warnings=on1865.4 C430的預(yù)定義符號1865.4.1 DATE1875.4.2 FILE1875.4.3 IAR_SYSTEMS_ICC1875.4.4 LINE1875.4.5 STDC1875.4.6 TID1875.4.7 TIME1885.4.8 VER1885.5 C430的本征函數(shù)1885.5.1 _args＄1885.5.2 _argt＄1895.5.3 _BIC_SR1895.5.4 _BIS_SR1905.5.5 _DINT1905.5.6 _EINT1905.5.7 _NOP1905.5.8 _OPC1905.6 C430的匯編語言接口1915.6.1 創(chuàng)建匯編子程序框架1915.6.2 調(diào)用規(guī)則1915.6.3 C程序調(diào)用匯編子程序1935.7 C430的段定義1935.7.1 存儲器分布與段定義1945.7.2 CCSTR段1945.7.3 CDATA0段1945.7.4 CODE段1955.7.5 CONST1955.7.6 CSTACK1955.7.7 CSTR1955.7.8 ECSTR1955.7.9 IDATA01965.7.10 INTVEC1965.7.11 NO_INIT1965.7.12 UDATA0196第6章 C430的庫函數(shù)6.1 引言1976.1.1 庫模塊文件1976.1.2 頭文件1976.1.3 庫定義匯總1976.2C 庫函數(shù)參考2046.2.1 C庫函數(shù)的說明格式2046.2.2 C庫函數(shù)說明204第7章 C430編譯器的診斷消息7.1 編譯診斷消息的類型2307.2 編譯出錯消息2317.3 編譯警告消息243附錄 AMSP430系列FLASH型芯片資料248附錄 BProF149實(shí)驗(yàn)系統(tǒng)251附錄 CMSP430x14x.H文件253附錄 DIAR MSP430 C語言產(chǎn)品介紹275
上傳時間： 2014-05-05
上傳用戶：253189838
This application note shows how to write an Inter Integrated Circuit bus driver (I²C) for the Philips P90CL301micro-controller.It is not only an example of writing a driver, but it also includes a set of application interface software routines toquickly implement a complete I²C multi-master system application.For specific applications the user will have to make minimal changes in the driver program. Using the drivermeans linking modules to your application software and including a header-file into the application sourceprograms. A small example program of how to use the driver is listed.The driver supports i.a. polled or interrupt driven message handling, slave message transfers and multi-mastersystem applications. Furthermore, it is made suitable for use in conjunction with real time operating systems, likepSOS+.
標(biāo)簽： routines driver P90 301
上傳時間： 2013-11-23
上傳用戶：weixiao99
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標(biāo)簽： Signal Input Fall Rise
上傳時間： 2013-10-23
上傳用戶：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上傳時間： 2014-04-02
上傳用戶：han_zh
I2C interface, is a very powerful tool for system designers. Theintegrated protocols allow systems to be completely software defined.Software development time of different products can be reduced byassembling a library of reusable software modules. In addition, themultimaster capability allows rapid testing and alignment ofend-products via external connections to an assembly-line computer.The mask programmable 87LPC76X and its EPROM version, the87LPC76X, can operate as a master or a slave device on the I2Csmall area network. In addition to the efficient interface to thededicated function ICs in the I2C family, the on-board interfacefacilities I/O and RAM expansion, access to EEPROM andprocessor-to-processor communications.
標(biāo)簽： microcontro Using 76X LPC
上傳時間： 2013-12-30
上傳用戶：Artemis
有兩種方式可以讓設(shè)備和應(yīng)用程序之間聯(lián)系：1. 通過為設(shè)備創(chuàng)建的一個符號鏈；2. 通過輸出到一個接口WDM驅(qū)動程序建議使用輸出到一個接口而不推薦使用創(chuàng)建符號鏈的方法。這個接口保證PDO的安全，也保證安全地創(chuàng)建一個惟一的、獨(dú)立于語言的訪問設(shè)備的方法。一個應(yīng)用程序使用Win32APIs來調(diào)用設(shè)備。在某個Win32 APIs和設(shè)備對象的分發(fā)函數(shù)之間存在一個映射關(guān)系。獲得對設(shè)備對象訪問的第一步就是打開一個設(shè)備對象的句柄。 用符號鏈打開一個設(shè)備的句柄為了打開一個設(shè)備，應(yīng)用程序需要使用CreateFile。如果該設(shè)備有一個符號鏈出口，應(yīng)用程序可以用下面這個例子的形式打開句柄：hDevice = CreateFile("\\\\.\\OMNIPORT3", GENERIC_READ | GENERIC_WRITE,FILE_SHARE_READ, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL ,NULL);文件路徑名的前綴“\\.\”告訴系統(tǒng)本調(diào)用希望打開一個設(shè)備。這個設(shè)備必須有一個符號鏈，以便應(yīng)用程序能夠打開它。有關(guān)細(xì)節(jié)查看有關(guān)Kdevice和CreateLink的內(nèi)容。在上述調(diào)用中第一個參數(shù)中前綴后的部分就是這個符號鏈的名字。注意：CreatFile中的第一個參數(shù)不是Windows 98/2000中驅(qū)動程序(.sys文件)的路徑。是到設(shè)備對象的符號鏈。如果使用DriverWizard產(chǎn)生驅(qū)動程序，它通常使用類KunitizedName來構(gòu)成設(shè)備的符號鏈。這意味著符號鏈名有一個附加的數(shù)字，通常是0。例如：如果鏈接名稱的主干是L“TestDevice”那么在CreateFile中的串就該是“\\\\.\\TestDevice0”。如果應(yīng)用程序需要被覆蓋的I/O，第六個參數(shù)(Flags)必須或上FILE_FLAG_OVERLAPPED。 使用一個輸出接口打開句柄用這種方式打開一個句柄會稍微麻煩一些。DriverWorks庫提供兩個助手類來使獲得對該接口的訪問容易一些，這兩個類是CDeviceInterface, 和 CdeviceInterfaceClass。CdeviceInterfaceClass類封裝了一個設(shè)備信息集，該信息集包含了特殊類中的所有設(shè)備接口信息。應(yīng)用程序能有用CdeviceInterfaceClass類的一個實(shí)例來獲得一個或更多的CdeviceInterface類的實(shí)例。CdeviceInterface類是一個單一設(shè)備接口的抽象。它的成員函數(shù)DevicePath()返回一個路徑名的指針，該指針可以在CreateFile中使用來打開設(shè)備。下面用一個小例子來顯示這些類最基本的使用方法：extern GUID TestGuid;HANDLE OpenByInterface( GUID* pClassGuid, DWORD instance, PDWORD pError){ CDeviceInterfaceClass DevClass(pClassGuid, pError); if (*pError != ERROR_SUCCESS) return INVALID_HANDLE_VALUE; CDeviceInterface DevInterface(&DevClass, instance, pError); if (*pError != ERROR_SUCCESS) return INVALID_HANDLE_VALUE; cout << "The device path is " << DevInterface.DevicePath() << endl; HANDLE hDev; hDev = CreateFile( DevInterface.DevicePath(), GENERIC_READ | GENERIC_WRITE, FILE_SHARE_READ | FILE_SHARE_WRITE, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL ); if (hDev == INVALID_HANDLE_VALUE) *pError = GetLastError(); return hDev;} 在設(shè)備中執(zhí)行I/O操作一旦應(yīng)用程序獲得一個有效的設(shè)備句柄，它就能使用Win32 APIs來產(chǎn)生到設(shè)備對象的IRPs。下面的表顯示了這種對應(yīng)關(guān)系。Win32 API DRIVER_FUNCTION_xxxIRP_MJ_xxx KDevice subclass member function CreateFile CREATE Create ReadFile READ Read WriteFile WRITE Write DeviceIoControl DEVICE_CONTROL DeviceControl CloseHandle CLOSECLEANUP CloseCleanUp 需要解釋一下設(shè)備類成員的Close和CleanUp：CreateFile使內(nèi)核為設(shè)備創(chuàng)建一個新的文件對象。這使得多個句柄可以映射同一個文件對象。當(dāng)這個文件對象的最后一個用戶級句柄被撤銷后，I/O管理器調(diào)用CleanUp。當(dāng)沒有任何用戶級和核心級的對文件對象的訪問的時候，I/O管理器調(diào)用Close。如果被打開的設(shè)備不支持指定的功能，則調(diào)用相應(yīng)的Win32將引起錯誤（無效功能）。以前為Windows95編寫的VxD的應(yīng)用程序代碼中可能會在打開設(shè)備的時候使用FILE_FLAG_DELETE_ON_CLOSE屬性。在Windows NT/2000中，建議不要使用這個屬性，因?yàn)樗鼘?dǎo)致沒有特權(quán)的用戶企圖打開這個設(shè)備，這是不可能成功的。I/O管理器將ReadFile和WriteFile的buff參數(shù)轉(zhuǎn)換成IRP域的方法依賴于設(shè)備對象的屬性。當(dāng)設(shè)備設(shè)置DO_DIRECT_IO標(biāo)志，I/O管理器將buff鎖住在存儲器中，并且創(chuàng)建了一個存儲在IRP中的MDL域。一個設(shè)備可以通過調(diào)用Kirp::Mdl來存取MDL。當(dāng)設(shè)備設(shè)置DO_BUFFERED_IO標(biāo)志，設(shè)備對象分別通過KIrp::BufferedReadDest或 KIrp::BufferedWriteSource為讀或?qū)懖僮鳙@得buff地址。當(dāng)設(shè)備不設(shè)置DO_BUFFERED_IO標(biāo)志也不設(shè)置DO_DIRECT_IO，內(nèi)核設(shè)置IRP 的UserBuffer域來對應(yīng)ReadFile或WriteFile中的buff參數(shù)。然而，存儲區(qū)并沒有被鎖住而且地址只對調(diào)用進(jìn)程有效。驅(qū)動程序可以使用KIrp::UserBuffer來存取IRP域。對于DeviceIoControl調(diào)用，buffer參數(shù)的轉(zhuǎn)換依賴于特殊的I/O控制代碼，它不在設(shè)備對象的特性中。宏CTL_CODE（在winioctl.h中定義）用來構(gòu)造控制代碼。這個宏的其中一個參數(shù)指明緩沖方法是METHOD_BUFFERED, METHOD_IN_DIRECT, METHOD_OUT_DIRECT, 或METHOD_NEITHER。下面的表顯示了這些方法和與之對應(yīng)的能獲得輸入緩沖與輸出緩沖的KIrp中的成員函數(shù)：Method Input Buffer Parameter Output Buffer Parameter METHOD_BUFFERED KIrp::IoctlBuffer KIrp::IoctlBuffer METHOD_IN_DIRECT KIrp::IoctlBuffer KIrp::Mdl METHOD_OUT_DIRECT KIrp::IoctlBuffer KIrp::Mdl METHOD_NEITHER KIrp::IoctlType3InputBuffer KIrp::UserBuffer 如果控制代碼指明METHOD_BUFFERED，系統(tǒng)分配一個單一的緩沖來作為輸入與輸出。驅(qū)動程序必須在向輸出緩沖放數(shù)據(jù)之前拷貝輸入數(shù)據(jù)。驅(qū)動程序通過調(diào)用KIrp::IoctlBuffer獲得緩沖地址。在完成時，I/O管理器從系統(tǒng)緩沖拷貝數(shù)據(jù)到提供給Ring 3級調(diào)用者使用的緩沖中。驅(qū)動程序必須在結(jié)束前存儲拷貝到IRP的Information成員中的數(shù)據(jù)個數(shù)。如果控制代碼不指明METHOD_IN_DIRECT或METHOD_OUT_DIRECT，則DeviceIoControl的參數(shù)呈現(xiàn)不同的含義。參數(shù)InputBuffer被拷貝到一個系統(tǒng)緩沖，這個緩沖驅(qū)動程序可以通過調(diào)用KIrp::IoctlBuffer。參數(shù)OutputBuffer被映射到KMemory對象，驅(qū)動程序?qū)@個對象的訪問通過調(diào)用KIrp::Mdl來實(shí)現(xiàn)。對于METHOD_OUT_DIRECT，調(diào)用者必須有對緩沖的寫訪問權(quán)限。注意，對METHOD_NEITHER，內(nèi)核只提供虛擬地址；它不會做映射來配置緩沖。虛擬地址只對調(diào)用進(jìn)程有效。這里是一個用METHOD_BUFFERED的例子：首先，使用宏CTL_CODE來定義一個IOCTL代碼：#define IOCTL_MYDEV_GET_FIRMWARE_REV \CTL_CODE (FILE_DEVICE_UNKNOWN,0,METHOD_BUFFERED,FILE_ANY_ACCESS)現(xiàn)在使用一個DeviceIoControl調(diào)用：BOOLEAN b;CHAR FirmwareRev[60];ULONG FirmwareRevSize;b = DeviceIoControl(hDevice, IOCTL_MYDEV_GET_VERSION_STRING, NULL, // no input 注意，這里放的是包含有執(zhí)行操作命令的字符串指針 0, FirmwareRev, //這里是output串指針，存放從驅(qū)動程序中返回的字符串。sizeof(FirmwareRev),& FirmwareRevSize, NULL // not overlapped I/O );如果輸出緩沖足夠大，設(shè)備拷貝串到里面并將拷貝的資結(jié)束設(shè)置到FirmwareRevSize中。在驅(qū)動程序中，代碼看起來如下所示：const char* FIRMWARE_REV = "FW 16.33 v5";NTSTATUS MyDevice::DeviceControl( KIrp I ){ ULONG fwLength=0; switch ( I.IoctlCode() ) { case IOCTL_MYDEV_GET_FIRMWARE_REV: fwLength = strlen(FIRMWARE_REV)+1; if (I.IoctlOutputBufferSize() >= fwLength) { strcpy((PCHAR)I.IoctlBuffer(),FIRMWARE_REV); I.Information() = fwLength; return I.Complete(STATUS_SUCCESS); } else { } case . . . } }
標(biāo)簽： 驅(qū)動程序 應(yīng)用程序 接口
上傳時間： 2013-10-17
上傳用戶：gai928943
針對使用硬件描述語言進(jìn)行設(shè)計存在的問題，提出一種基于FPGA并采用DSP Builder作為設(shè)計工具的數(shù)字信號處理器設(shè)計方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ設(shè)計流程，設(shè)計了一個12階FIR 低通數(shù)字濾波器，通過Quartus 時序仿真及嵌入式邏輯分析儀SignalTapⅡ硬件測試對設(shè)計進(jìn)行了驗(yàn)證。結(jié)果表明，所設(shè)計的FIR 濾波器功能正確，性能良好。 Abstract: Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
標(biāo)簽： Builder FPGA DSP 數(shù)字信號處理器
上傳時間： 2013-11-17
上傳用戶：lo25643
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
Verilog_HDL的基本語法詳解（夏宇聞版）:Verilog HDL是一種用于數(shù)字邏輯電路設(shè)計的語言。用Verilog HDL描述的電路設(shè)計就是該電路的Verilog HDL模型。Verilog HDL既是一種行為描述的語言也是一種結(jié)構(gòu)描述的語言。這也就是說，既可以用電路的功能描述也可以用元器件和它們之間的連接來建立所設(shè)計電路的Verilog HDL模型。Verilog模型可以是實(shí)際電路的不同級別的抽象。這些抽象的級別和它們對應(yīng)的模型類型共有以下五種： 系統(tǒng)級（system）：用高級語言結(jié)構(gòu)實(shí)現(xiàn)設(shè)計模塊的外部性能的模型。 算法級（algorithm）：用高級語言結(jié)構(gòu)實(shí)現(xiàn)設(shè)計算法的模型。 RTL級（Register Transfer Level）：描述數(shù)據(jù)在寄存器之間流動和如何處理這些數(shù)據(jù)的模型。 門級（gate-level）：描述邏輯門以及邏輯門之間的連接的模型。 開關(guān)級（switch-level）：描述器件中三極管和儲存節(jié)點(diǎn)以及它們之間連接的模型。 一個復(fù)雜電路系統(tǒng)的完整Verilog HDL模型是由若干個Verilog HDL模塊構(gòu)成的，每一個模塊又可以由若干個子模塊構(gòu)成。其中有些模塊需要綜合成具體電路，而有些模塊只是與用戶所設(shè)計的模塊交互的現(xiàn)存電路或激勵信號源。利用Verilog HDL語言結(jié)構(gòu)所提供的這種功能就可以構(gòu)造一個模塊間的清晰層次結(jié)構(gòu)來描述極其復(fù)雜的大型設(shè)計，并對所作設(shè)計的邏輯電路進(jìn)行嚴(yán)格的驗(yàn)證。 Verilog HDL行為描述語言作為一種結(jié)構(gòu)化和過程性的語言，其語法結(jié)構(gòu)非常適合于算法級和RTL級的模型設(shè)計。這種行為描述語言具有以下功能： · 可描述順序執(zhí)行或并行執(zhí)行的程序結(jié)構(gòu)。 · 用延遲表達(dá)式或事件表達(dá)式來明確地控制過程的啟動時間。 · 通過命名的事件來觸發(fā)其它過程里的激活行為或停止行為。 · 提供了條件、if-else、case、循環(huán)程序結(jié)構(gòu)。 · 提供了可帶參數(shù)且非零延續(xù)時間的任務(wù)（task）程序結(jié)構(gòu)。 · 提供了可定義新的操作符的函數(shù)結(jié)構(gòu)（function）。 · 提供了用于建立表達(dá)式的算術(shù)運(yùn)算符、邏輯運(yùn)算符、位運(yùn)算符。 · Verilog HDL語言作為一種結(jié)構(gòu)化的語言也非常適合于門級和開關(guān)級的模型設(shè)計。因其結(jié)構(gòu)化的特點(diǎn)又使它具有以下功能： - 提供了完整的一套組合型原語（primitive）; - 提供了雙向通路和電阻器件的原語; - 可建立MOS器件的電荷分享和電荷衰減動態(tài)模型。 Verilog HDL的構(gòu)造性語句可以精確地建立信號的模型。這是因?yàn)樵赩erilog HDL中，提供了延遲和輸出強(qiáng)度的原語來建立精確程度很高的信號模型。信號值可以有不同的的強(qiáng)度，可以通過設(shè)定寬范圍的模糊值來降低不確定條件的影響。 Verilog HDL作為一種高級的硬件描述編程語言，有著類似C語言的風(fēng)格。其中有許多語句如：if語句、case語句等和C語言中的對應(yīng)語句十分相似。如果讀者已經(jīng)掌握C語言編程的基礎(chǔ)，那么學(xué)習(xí)Verilog HDL并不困難，我們只要對Verilog HDL某些語句的特殊方面著重理解，并加強(qiáng)上機(jī)練習(xí)就能很好地掌握它，利用它的強(qiáng)大功能來設(shè)計復(fù)雜的數(shù)字邏輯電路。下面我們將對Verilog HDL中的基本語法逐一加以介紹。
標(biāo)簽： Verilog_HDL
上傳時間： 2013-11-23
上傳用戶：青春給了作業(yè)95
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