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mixed-Timing

timing,原程序及testbench,供初學(xué)者參考

timing,原程序及testbench,供初學(xué)者參考

標(biāo)簽： testbench timing 程序初學(xué)者

上傳時(shí)間： 2013-12-22

上傳用戶(hù)：chfanjiang
Altera Quartusii靜態(tài)時(shí)序分析（Static Timing Analysis）基礎(chǔ)及應(yīng)用

Altera Quartusii靜態(tài)時(shí)序分析（Static Timing Analysis）基礎(chǔ)及應(yīng)用

標(biāo)簽： Quartusii Analysis Altera Static

上傳時(shí)間： 2014-01-26

上傳用戶(hù)：a6697238
Static Timing Analyzer

Static Timing Analyzer

標(biāo)簽： Analyzer Static Timing

上傳時(shí)間： 2013-12-12

上傳用戶(hù)：sxdtlqqjl
VESA VIDEO TIMING BLOCK EXTENSION DATA STANDARD VTB-EXT Standard 求edid2.0

VESA VIDEO TIMING BLOCK EXTENSION DATA STANDARD VTB-EXT Standard 求edid2.0

標(biāo)簽： EXTENSION STANDARD Standard VTB-EXT

上傳時(shí)間： 2014-12-05

上傳用戶(hù)：wpwpwlxwlx
Describes ISO14230 vehicle communication protocol, signals, timing, data exhange.

Describes ISO14230 vehicle communication protocol, signals, timing, data exhange.

標(biāo)簽： communication Describes protocol vehicle

上傳時(shí)間： 2014-01-11

上傳用戶(hù)：cuiyashuo
QVGA的Timing verilog 描述

QVGA的Timing verilog 描述

標(biāo)簽： verilog Timing QVGA

上傳時(shí)間： 2016-02-11

上傳用戶(hù)：Avoid98
CP detector (CPD) only reports the onset and removal of a tone. The analysis of timing (if required)

CP detector (CPD) only reports the onset and removal of a tone. The analysis of timing (if required) shall be responsibility of a higher-level application due to uncontrollable variability of those parameters from country to country.FOR TI C54X/C55X

標(biāo)簽： detector analysis required reports

上傳時(shí)間： 2013-12-02

上傳用戶(hù)：ynsnjs
CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification re

CF VHDL The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices ADSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.

標(biāo)簽： specification the designed diagrams

上傳時(shí)間： 2013-12-27

上傳用戶(hù)：yyyyyyyyyy
Analog and Mixed-Signal Modeling Using the VHDL-AMS Language

Analog and Mixed-Signal Modeling Using the VHDL-AMS Language

標(biāo)簽： Mixed-Signal Language Modeling VHDL-AMS

上傳時(shí)間： 2016-04-13

上傳用戶(hù)：ZJX5201314
This is a paper of "a rbust timing and freqeuncy synchronization for ofdm systems"

This is a paper of "a rbust timing and freqeuncy synchronization for ofdm systems"

標(biāo)簽： synchronization freqeuncy systems timing

上傳時(shí)間： 2013-12-21

上傳用戶(hù)：zmy123

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