針對(duì)當(dāng)前安檢力學(xué)試驗(yàn)機(jī)所能完成的試驗(yàn)種類單一、自動(dòng)化程度低等問題，提出一種以ATmega128單片機(jī)為核心控制器的安檢力學(xué)試驗(yàn)機(jī)的設(shè)計(jì)。詳細(xì)闡述了該安檢力學(xué)試驗(yàn)機(jī)各個(gè)組成部分的設(shè)計(jì)原理和方案，并且給出了各部分的軟件設(shè)計(jì)思想和操作流程。經(jīng)過大量測(cè)試試驗(yàn)表明：設(shè)計(jì)的安檢力學(xué)試驗(yàn)機(jī)可以完成多達(dá)十余種的力學(xué)安檢試驗(yàn)，完全符合相關(guān)國家標(biāo)準(zhǔn)，并且具有數(shù)據(jù)采集精度高、傳輸速度快、操作安全簡便等特點(diǎn)，實(shí)現(xiàn)了安檢設(shè)備的多功能化、數(shù)字化和自動(dòng)化。 Abstract: Currently， many mechanical security testing machines have only one function. The degree of automation of them is low. To solve those problems， a new kind of mechanical security testing machine， using ATmega128 micro-controller as its core controller， has been advanced. It describes the components of the machine. The principles and the scheme in the designing processes are presented in detail， and the software architecture and the operation processes of each part are given. After having done many testing， we have reached the following conclusions: the mechanical security testing machine presented can do over ten mechanical security tests complying with related national standards. It has high data acquisition accuracy and high transmission speed. The operation of the machine is simple and safe. In general， this machine is a multi-functional， highly automatic， digitalized security testing device.
標(biāo)簽： ATmega 128 安檢 試驗(yàn)機(jī)
上傳時(shí)間： 2013-11-05
上傳用戶：a67818601
雖然PIC都是8位的單片機(jī)，但都采用RISC（Reduced Instruction Set Computing）核心結(jié)構(gòu)，這有別于過去一般的CISC(Complex Instruction Set Computing)結(jié)構(gòu)。所謂RISC結(jié)構(gòu)就是采用哈佛雙總線結(jié)構(gòu)，將地址總線與數(shù)據(jù)總線分開，因此在同一個(gè)指令執(zhí)行過程中，數(shù)據(jù)與地址可以同時(shí)傳送，避免了總線處理上的瓶頸。
上傳時(shí)間： 2013-11-21
上傳用戶：tianyi223
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對(duì)移相（QDPSK)信號(hào)調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺(tái)上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測(cè)試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計(jì)
上傳時(shí)間： 2014-01-13
上傳用戶：qoovoop
Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the VSIA Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.
上傳時(shí)間： 2014-01-24
上傳用戶：xinhaoshan2016
云計(jì)算（cloud computing）中涉及了分布式處理、并行處理和網(wǎng)格計(jì)算、網(wǎng)絡(luò)存儲(chǔ)、虛擬化、負(fù)載均衡等傳統(tǒng)計(jì)算機(jī)技術(shù)和網(wǎng)絡(luò)技術(shù)。本文從云計(jì)算的體系架構(gòu)和服務(wù)角度出發(fā)，對(duì)云計(jì)算中實(shí)現(xiàn)的訪問控制管理、數(shù)據(jù)管理和虛擬化功能所使用加密算法和虛擬化等關(guān)鍵技術(shù)，用計(jì)算機(jī)和網(wǎng)絡(luò)知識(shí)分析了這些技術(shù)存在的問題，提出了需要改進(jìn)的方向。
標(biāo)簽： 云計(jì)算 關(guān)鍵技術(shù)
上傳時(shí)間： 2013-10-16
上傳用戶：陽光少年2016
Abstract: Field-programmable gate arrays (FPGAs) are used in a wide variety of applications and end markets, including digital signalprocessing, medical imaging, and high-performance computing. This application note outlines the issues related to powering FPGAs.It also discusses Maxim's solutions for powering Xilinx® FPGAs.
上傳時(shí)間： 2013-12-16
上傳用戶：haohaoxuexi
This book is about the digital logic design of microprocessors. It is intended to provide both an understanding of the basic principles of digital logic design, and how these fundamental principles are applied in the building of complex microprocessor circuits using current technologies.
上傳時(shí)間： 2013-10-14
上傳用戶：leyesome
OpenCLOpenCL（全稱Open Computing Language，開放運(yùn)算語言）是第一個(gè)面向異構(gòu)系統(tǒng)通用目的并行編程的開放式、免費(fèi)標(biāo)準(zhǔn)，也是一個(gè)統(tǒng)一的編程環(huán)境，便于軟件開發(fā)人員為高性能計(jì)算服務(wù)器、桌面計(jì)算系統(tǒng)、手持設(shè)備編寫高效輕便的代碼，而且廣泛適用于多核心處理器(CPU)、圖形處理器(GPU)、Cell類型架構(gòu)以及數(shù)字信號(hào)處理器(DSP)等其他并行處理器，在游戲、娛樂、科研、醫(yī)療等各種領(lǐng)域都有廣闊的發(fā)展前景。
標(biāo)簽： OpenCL 48 CN 開放運(yùn)算
上傳時(shí)間： 2014-12-31
上傳用戶：netwolf
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對(duì)移相（QDPSK)信號(hào)調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺(tái)上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測(cè)試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計(jì)
上傳時(shí)間： 2013-10-28
上傳用戶：jyycc
Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the VSIA Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.
上傳時(shí)間： 2013-11-19
上傳用戶：m62383408
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