Using Compiler-inserted Releases to Manage Physical Memory Intelligently∗
標(biāo)簽： Compiler-inserted Intelligently Releases Physical
上傳時(shí)間： 2014-01-18
上傳用戶：thinode
this file can copy the files in the removable disks when the disk is inserted into the system
標(biāo)簽： the removable inserted system
上傳時(shí)間： 2014-01-08
上傳用戶：edisonfather
It is inserted that the worm will duplicate great.exe to get the systematic materials in the computer of infecting, and produce a script.ini file to reach in mirc catalogue . The worm will utilize emule to disseminate too.
標(biāo)簽： the systematic duplicate materials
上傳時(shí)間： 2017-01-13
上傳用戶：ddddddos
匯編器在微處理器的驗(yàn)證和應(yīng)用中舉足輕重，如何設(shè)計(jì)通用的匯編器一直是研究的熱點(diǎn)之一。本文提出了一種開(kāi)放式的匯編器系統(tǒng)設(shè)計(jì)思想，在匯編語(yǔ)言與機(jī)器語(yǔ)言間插入中間代碼CMDL（code mapping description language）語(yǔ)言，打破匯編語(yǔ)言與機(jī)器語(yǔ)言的直接映射關(guān)系，由此建立起一套描述匯編語(yǔ)言與機(jī)器語(yǔ)言的開(kāi)放式映射體系。基于此開(kāi)放式映射體系開(kāi)發(fā)了一套匯編器系統(tǒng)，具有較高層次上的通用性和可移植性。【關(guān)鍵詞】指令集，CMDL，匯編器，開(kāi)放式 Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【關(guān)鍵詞】instruction set, symbol table, assembler, lexical analysis, retargetability
上傳時(shí)間： 2013-10-10
上傳用戶：meiguiweishi
工具分類：攻擊程序 運(yùn)行平臺(tái)：Windows 工具大小：7577 Bytes 文件MD5 ：28f6d5f4d818438522a3d0dc8a3fa46b 工具來(lái)源：securiteam.com // GDI+ buffer overrun exploit by FoToZ // NB: the headers here are only sample headers taken from a .JPG file, // with the FF FE 00 01 inserted in header1. // Sample shellcode is provided // You can put approx. 2500 bytes of shellcode...who needs that much anyway // Tested on an unpatched WinXP SP1
標(biāo)簽： 818438522a d818438522 securiteam 818438522
上傳時(shí)間： 2015-01-20
上傳用戶：Late_Li
TOYFDTD1 is a stripped-down minimalist, 3D FDTD code demonstrating the basic tasks in implementing a simple 3D FDTD simulation. An idealized rectangular waveguide is modeled by treating the interior of the mesh as free space and enforcing PEC conditions on the faces of the mesh. A simplified plane wave source is inserted at one end. First released 12 April 1999. Version 1.03 released 2 December 1999.
標(biāo)簽： demonstrating stripped-down implementing minimalist
上傳時(shí)間： 2013-12-21
上傳用戶：無(wú)聊來(lái)刷下
關(guān)于FPGA流水線設(shè)計(jì)的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標(biāo)簽： investigates implementing pipelines circuits
上傳時(shí)間： 2015-07-26
上傳用戶：CHINA526
This program generates OFDM (Orthogonal Frequency Division Multiplexing) signal and its spectrum. Also the guard interval (GI) is inserted.
標(biāo)簽： Multiplexing Orthogonal Frequency generates
上傳時(shí)間： 2014-01-16
上傳用戶：daoxiang126
Blink cell or colouring cell.The used of this table ,it can let user know that new data was insert. The cell wil blink when new data is inserted.
標(biāo)簽： cell colouring insert Blink
上傳時(shí)間： 2017-08-19
上傳用戶：VRMMO
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