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  • MAX338/MAX339的英文數據手冊

      本軟件是關于MAX338, MAX339的英文數據手冊:MAX338, MAX339   8通道/雙4通道、低泄漏、CMOS模擬多路復用器   The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions.   These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.

    標簽: MAX 338 339 英文

    上傳時間: 2013-11-12

    上傳用戶:18711024007

  • 使用Artix-7 FPGA 降低您的系統功耗與成本

    As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-power,cost-sensitive markets. Application classes like

    標簽: Artix FPGA 功耗

    上傳時間: 2013-11-08

    上傳用戶:immanuel2006

  • 采用TüV認證的FPGA開發功能安全系統

    This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System

    標簽: FPGA 安全系統

    上傳時間: 2013-11-14

    上傳用戶:zoudejile

  • wp379 AXI4即插即用IP

    In the past decade, the size and complexity of manyFPGA designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting challenge that often extends, rather thanshortens, design time. As today's designs integrateincreasing amounts of functionality, it is vital thatdesigners have access to proven, up-to-date IP fromreliable sources.

    標簽: AXI4 379 wp 即插即用

    上傳時間: 2013-11-11

    上傳用戶:csgcd001

  • WP401-FPGA設計的DO-254

    The standard that governs the design of avioniccomponents and systems, DO-254, is one of the mostpoorly understood but widely applicable standardsin the avionic industry. While information on thegeneral aspects of the standard is easy to obtain, thedetails of exactly how to implement the standard aresketchy. And once an entity develops a process thatachieves compliance, the details of how compliancewas achieved become part of the intellectualproperty of that entity. This white paper focuses onthe details of developing a DO-254 compliantprocess for the design of FPGAs.

    標簽: FPGA 401 254 WP

    上傳時間: 2013-11-03

    上傳用戶:ysystc670

  • WP196-平面顯示器中的Xilinx器件

      According to CIBC World Markets, Equity Research, theFlat Panel Display (FPD) industry has achieved sufficientcritical mass for its growth to explode. Thus, it can nowattract the right blend of capital investments and R&Dresources to drive technical innovation toward continuousimprovement in view quality, manufacturing efficiency,and system integration. These in turn are sustainingconsumer interest, penetration, revenue growth, and thepotential for increasing long-term profitability for industryparticipants. CIBC believes that three essential conditionsare now converging to drive the market forward

    標簽: Xilinx 196 WP 平面顯示器

    上傳時間: 2015-01-02

    上傳用戶:小楓殘月

  • Virtex-5 GTP Transceiver Wizar

    The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts

    標簽: Transceiver Virtex Wizar GTP

    上傳時間: 2013-10-20

    上傳用戶:dave520l

  • 賽靈思電機控制開發套件簡介(英文版)

      The power of programmability gives industrial automation designers a highly efficient, cost-effective alternative to traditional motor control units (MCUs)。 The parallel-processing power, fast computational speeds, and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control (FOC)。   Additionally, Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing (DSP) that can tackle compute-intensive functions such as PID Controller, Clark/Park transforms, and Space Vector PWM.   The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving, proven, motor-control reference designs. The kit also shortens the process of developing custom control capabilities, with integrated peripheral functions (Ethernet, PowerLink, and PCI® Express), a motor-control FPGA mezzanine card (FMC) with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators, and prototyping support for evaluating alternative front-end circuitry.

    標簽: 賽靈思 電機控制 開發套件 英文

    上傳時間: 2013-10-28

    上傳用戶:wujijunshi

  • ISA(PC104)總線規范

    ISA總線概述   ISA總線: (Industry Standard Architecture:工業標準體系結構)是IBM公司為PC/AT電腦而制定的總線標準,為16位體系結構,只能支持16位的I/O設備,數據傳輸率大約是16MB/S。也稱為AT標準。開始時PC機面向個人及辦公室,定義了8位的ISA總線結構,對外公開,成為標準(ISO ISA標準)。第三方開發出許多ISA擴充板卡,推動了PC機的發展。1984年推出IBM-PC/AT系統,ISA從8位擴充到16位,地址線從20條擴充到24條。1988年,康柏、HP、NEC等9個廠商協同把ISA擴展到32位,即EISA總線(Extended ISA)。

    標簽: ISA 104 PC 總線規范

    上傳時間: 2013-10-16

    上傳用戶:dajin

  • CGAL is a collaborative effort of several sites in Europe and Israel. The goal is to make the most i

    CGAL is a collaborative effort of several sites in Europe and Israel. The goal is to make the most important of the solutions and methods developed in computational geometry available to users in industry and academia in a C++ library. The goal is to provide easy access to useful, reliable geometric algorithms

    標簽: collaborative several Europe Israel

    上傳時間: 2015-01-09

    上傳用戶:refent

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