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hierarchical

  • Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

    Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical and the sub-circuits can be used as smaller benchmarks.

    標(biāo)簽: Stereo-Vision description Darabiha contains

    上傳時(shí)間: 2017-03-19

    上傳用戶:comua

  • AHP toolbox AHPCALC Perform a complete AHP calculation. AHPHIER One-step hierarchic

    AHP toolbox AHPCALC Perform a complete AHP calculation. AHPHIER One-step hierarchical assembly of AHP weighting vector. AHPREORDER Internal reordering function called by AHPCALC. AHPVECTOR Calculate the AHP ranking or weighting vector from an AHP reciproal matrix. AHPMAKEMAT Turn a vector of comparisons into an AHP reciprocal matrix. Copyright (C) 2001 Michael J. Scott

    標(biāo)簽: calculation hierarchic AHP One-step

    上傳時(shí)間: 2013-11-28

    上傳用戶:PresidentHuang

  • 基于頻率插值的4.0kbps 語音編碼器的性能和設(shè)計(jì)(英文)

    The 4.0 kbit/s speech codec described in this paper is based on a Frequency Domain Interpolative (FDI) coding technique, which belongs to the class of prototype waveform Interpolation (PWI) coding techniques. The codec also has an integrated voice activity detector (VAD) and a noise reduction capability. The input signal is subjected to LPC analysis and the prediction residual is separated into a slowly evolving waveform (SEW) and a rapidly evolving waveform (REW) components. The SEW magnitude component is quantized using a hierarchical predictive vector quantization approach. The REW magnitude is quantized using a gain and a sub-band based shape. SEW and REW phases are derived at the decoder using a phase model, based on a transmitted measure of voice periodicity. The spectral (LSP) parameters are quantized using a combination of scalar and vector quantizers. The 4.0 kbits/s coder has an algorithmic delay of 60 ms and an estimated floating point complexity of 21.5 MIPS. The performance of this coder has been evaluated using in-house MOS tests under various conditions such as background noise. channel errors, self-tandem. and DTX mode of operation, and has been shown to be statistically equivalent to ITU-T (3.729 8 kbps codec across all conditions tested.

    標(biāo)簽: frequency-domain interpolation performance Design kbit_s speech coder based and of

    上傳時(shí)間: 2018-04-08

    上傳用戶:kilohorse

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