Proteus simulation of graphical lcd
標(biāo)簽： simulation graphical Proteus lcd
上傳時間： 2013-09-25
上傳用戶：lyy1234
the practice of proteus and avr
標(biāo)簽： practice proteus the and
上傳時間： 2013-09-29
上傳用戶：tom_man2008
Abstract: Specifications such as noise, effective number of bits (ENOB), effective resolution, and noise-free resolution inlarge part define how accurate an ADC really is. Consequently, understanding the performance metrics related to noise isone of the most difficult aspects of transitioning from a SAR to a delta-sigma ADC. With the current demand for higherresolution, designers must develop a better understanding of ADC noise, ENOB, effective resolution, and signal-to-noiseratio (SNR). This application note helps that understanding.
標(biāo)簽： ENOB 模數(shù)轉(zhuǎn)換器
上傳時間： 2013-10-16
上傳用戶：x18010875091
The LT®6552 is a specialized dual-differencing 75MHzoperational amplifier ideal for rejecting common modenoise as a video line receiver. The input pairs are designedto operate with equal but opposite large-signal differencesand provide exceptional high frequency commonmode rejection (CMRR of 65dB at 10MHz), therebyforming an extremely versatile gain block structure thatminimizes component count in most situations. The dualinput pairs are free to take on independent common modelevels, while the two voltage differentials are summedinternally to form a net input signal.
上傳時間： 2014-12-23
上傳用戶：13691535575
Most circuit designers are familiar with diode dynamiccharacteristics such as charge storage, voltage dependentcapacitance and reverse recovery time. Less commonlyacknowledged and manufacturer specifi ed is diode forwardturn-on time. This parameter describes the timerequired for a diode to turn on and clamp at its forwardvoltage drop. Historically, this extremely short time, unitsof nanoseconds, has been so small that user and vendoralike have essentially ignored it. It is rarely discussed andalmost never specifi ed. Recently, switching regulator clockrate and transition time have become faster, making diodeturn-on time a critical issue. Increased clock rates aremandated to achieve smaller magnetics size; decreasedtransition times somewhat aid overall effi ciency but areprincipally needed to minimize IC heat rise. At clock speedsbeyond about 1MHz, transition time losses are the primarysource of die heating.
標(biāo)簽： 二極管 導(dǎo)通 開關(guān)穩(wěn)壓器
上傳時間： 2013-10-10
上傳用戶：誰偷了我的麥兜
Construction Strategy of ESD Protection CircuitAbstract： The principles used to construct ESD protection on circuits and the basic conceptions of ESD protection design are presented.Key words：ESD protection/On circuit, ESD design window, ESD current path1 引言靜電放電（ESD，Electrostatic Discharge）給電子器件環(huán)境會帶來破壞性的后果。它是造成集成電路失效的主要原因之一。隨著集成電路工藝不斷發(fā)展，互補(bǔ)金屬氧化物半導(dǎo)體（CMOS，Complementary Metal-Oxide Semiconductor）的特征尺寸不斷縮小，金屬氧化物半導(dǎo)體(MOS, Metal-Oxide Semiconductor)的柵氧厚度越來越薄，MOS 管能承受的電流和電壓也越來越小，因此要進(jìn)一步優(yōu)化電路的抗ESD 性能，需要從全芯片ESD 保護(hù)結(jié)構(gòu)的設(shè)計來進(jìn)行考慮。
標(biāo)簽： Construction Strategy ESD of
上傳時間： 2013-11-09
上傳用戶：Aidane
模擬集成電路的設(shè)計與其說是一門技術(shù)，還不如說是一門藝術(shù)。它比數(shù)字集成電路設(shè)計需要更嚴(yán)格的分析和更豐富的直覺。嚴(yán)謹(jǐn)堅實(shí)的理論無疑是嚴(yán)格分析能力的基石，而設(shè)計者的實(shí)踐經(jīng)驗(yàn)無疑是誕生豐富直覺的源泉。這也正足初學(xué)者對學(xué)習(xí)模擬集成電路設(shè)計感到困惑并難以駕馭的根本原因。.美國加州大學(xué)洛杉機(jī)分校(UCLA)Razavi教授憑借著他在美國多所著名大學(xué)執(zhí)教多年的豐富教學(xué)經(jīng)驗(yàn)和在世界知名頂級公司(AT&T，Bell Lab，HP)卓著的研究經(jīng)歷為我們提供了這本優(yōu)秀的教材。本書自2000午出版以來得到了國內(nèi)外讀者的好評和青睞，被許多國際知名大學(xué)選為教科書。同時，由于原著者在世界知名頂級公司的豐富研究經(jīng)歷，使本書也非常適合作為CMOS模擬集成電路設(shè)計或相關(guān)領(lǐng)域的研究人員和工程技術(shù)人員的參考書。... 本書介紹模擬CMOS集成電路的分析與設(shè)計。從直觀和嚴(yán)密的角度闡述了各種模擬電路的基本原理和概念，同時還闡述了在SOC中模擬電路設(shè)計遇到的新問題及電路技術(shù)的新發(fā)展。本書由淺入深，理論與實(shí)際結(jié)合，提供了大量現(xiàn)代工業(yè)中的設(shè)計實(shí)例。全書共18章。前10章介紹各種基本模塊和運(yùn)放及其頻率響應(yīng)和噪聲。第11章至第13章介紹帶隙基準(zhǔn)、開關(guān)電容電路以及電路的非線性和失配的影響，第14、15章介紹振蕩器和鎖相環(huán)。第16章至18章介紹MOS器件的高階效應(yīng)及其模型、CMOS制造工藝和混合信號電路的版圖與封裝。 1 Introduction to Analog Design 2 Basic MOS Device Physics 3 Single-Stage Amplifiers 4 Differential Amplifiers 5 Passive and Active Current Mirrors 6 Frequency Response of Amplifiers 7 Noise 8 Feedback 9 Operational Amplifiers 10 Stability and Frequency Compensation 11 Bandgap References 12 Introduction to Switched-Capacitor Circuits 13 Nonlinearity and Mismatch 14 Oscillators 15 Phase-Locked Loops 16 Short-Channel Effects and Device Models 17 CMOS Processing Technology 18 Layout and Packaging
標(biāo)簽： analog design cmos of
上傳時間： 2014-12-23
上傳用戶：杜瑩12345
2400W-SPWM驅(qū)動電路，Backup of 修改2400W-SPWM驅(qū)動電路。
標(biāo)簽： Backup W-SPWM 2400 of
上傳時間： 2013-11-14
上傳用戶：dddddd
在 charge 項(xiàng)目中升壓部分的總結(jié)。
標(biāo)簽： charge 項(xiàng)目 升壓 分
上傳時間： 2013-12-19
上傳用戶：ippler8
Abstract: We don't expect manufacturers to produce clothes that in one size that fits everyone. In thesame way, one ESD component can't solve all issues—each application has different ESD requirements.Knowing that "one size fits all" cannot apply to power design, the power designer, or the engineering"super hero," must consider all the potential disruptions to a steady flow of power and thenvarious waysto mitigate them. This tutorial describes voltage- and current-limiting devices and risetime reducers tomanage the power. It also points to free and low-cost software tools to help design lowpass filters, checkcapacitor self-resonance, and simulate circuits.
上傳時間： 2013-11-18
上傳用戶：zhouxuepeng1
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