last time when i came here to find some clock references. but most of them can not works well. so this files works well on FPGA board.
標(biāo)簽： references clock works last
上傳時(shí)間： 2015-11-07
上傳用戶：baitouyu
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
標(biāo)簽： Spartan XAPP FPGA 098
上傳時(shí)間： 2014-08-16
上傳用戶：adada
針對(duì)傳統(tǒng)集成電路（ASIC）功能固定、升級(jí)困難等缺點(diǎn)，利用FPGA實(shí)現(xiàn)了擴(kuò)頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實(shí)現(xiàn)NCO模塊，在下變頻模塊調(diào)用了硬核乘法器并引入CIC濾波器進(jìn)行低通濾波，給出了DQPSK解調(diào)的原理和實(shí)現(xiàn)方法，推導(dǎo)出一種簡便的引入?仔/4固定相移的實(shí)現(xiàn)方法。采用模塊化的設(shè)計(jì)方法使用VHDL語言編寫出源程序，在Virtex-II Pro 開發(fā)板上成功實(shí)現(xiàn)了整個(gè)系統(tǒng)。測試結(jié)果表明該系統(tǒng)正確實(shí)現(xiàn)了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
標(biāo)簽： STEL 2000 FPGA 擴(kuò)頻通信
上傳時(shí)間： 2013-11-06
上傳用戶：liu123
Raggedstone1 IP core. Raggedstone1 is a low-cost Spartan3 FPGA based PCI development board made by Enterpoint Ltd.
標(biāo)簽： Raggedstone1 development Spartan3 low-cost
上傳時(shí)間： 2013-12-02
上傳用戶：lps11188
資料共6.37G，Xilinx Z-turn Board zynq7020平臺(tái)，包括FPGA、SDK源碼，例程源碼，各種圖像處理，人工智能算法，原理圖，PCB，適合做項(xiàng)目移植、項(xiàng)目開發(fā)
標(biāo)簽： fpga xilinx zynq7020 開發(fā)板
上傳時(shí)間： 2021-12-20
上傳用戶：
利用FPGA的51 ，IP核實(shí)現(xiàn)與單片機(jī)和ARM的串口通信
上傳時(shí)間： 2013-08-05
上傳用戶：lalaruby
基于FPGA數(shù)字頻率計(jì)的實(shí)現(xiàn)，文中有所有的源代碼，僅供參考。
標(biāo)簽： FPGA 數(shù)字頻率計(jì)
上傳時(shí)間： 2013-08-05
上傳用戶：13736136189
學(xué)習(xí)FPGA的不錯(cuò)的文章,有利于自己設(shè)計(jì)和編寫程序
標(biāo)簽： FPGA
上傳時(shí)間： 2013-08-05
上傳用戶：xjz632
基FPGA Cyclone II_EP2C5 EP2C8的頻率計(jì)
標(biāo)簽： Cyclone EP2C8 II_EP FPGA
上傳時(shí)間： 2013-08-05
上傳用戶：Thuan
波束成型，基于FPGA的波束成型，包括兩個(gè)文件，一個(gè)濾波器，一個(gè)xilinx仿真
上傳時(shí)間： 2013-08-05
上傳用戶：joheace
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