ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
上傳時間： 2013-11-12
上傳用戶：pans0ul
The equal-area theorem●This is sinusoidal PWM (SPWM)●The equal-area theorem can be appliedto realize any shape of waveforms ●Natural sampling●Calculation based on equal-area criterion●Selected harmonic elimination●Regular sampling●Hysteresis-band control●Triangular wave comparison withfeedback control
上傳時間： 2013-11-22
上傳用戶：linyao
該系統由單片機89S52控制模塊，程控寬帶放大模塊，整形模塊，FPGA內頻率、相位差測量模塊等構成，采用等精度測頻法測出頻率和周期，可測量有效值為0.01～5V，頻率范圍1Hz～20MHz信號的頻率、周期信號，精度高達10-6。采用計數法測量相位差，該系統可測量有效值0.5～5V，頻率10Hz～100kHz信號的相位差，精度為1°。系統功能由按鍵控制，測量結果實時顯示，人機界面友好。 Abstract: The system consists of the following functional blocks:89S52microcontroller controlling module,programmable amplifier module,comparator module,frequency and phase difference testing module in the FPGA.The system use the equal accuracy frequency-examining technique it measures frequency and circle of signal which its ranges is from1Hz to20MHz and the amplitude of which its range is from0.01Vrms to5Vrms,precision is up to10-6.Using of count method,the system detects the phase difference of signal,the amplitude of whic its range is from0.5Vrms to5Vrms and the frequency of which its ranges is from10Hz to100kHz,precision is up to1°,The system functions is controlled by certain keys,measurement results are displayed in real-time and it is friendly interface.
上傳時間： 2013-11-04
上傳用戶：CHINA526
以89S52單片機和EP1C6Q240C8型FPGA為控制核心的多功能計數器，是由峰值檢波、A/D轉換、程控放大、比較整形、移相網絡部分組成,可實現測量正弦信號的頻率、周期和相位差的功能。多功能計數器采用等精度的測量方法，可實現頻率為1Hz～10MHz、幅度為0.01～5Vrms的正弦信號的精確測頻，以及頻率為10Hz～100kHz、幅度為0.5～5Vrms的正弦信號精確測相。液晶顯示器能夠實時顯示當前信號的頻率、周期和相位差。該多功能計數器精度高，界面友好，實用性強。 Abstract: A multi-function counter，which uses89S52MCU and EP1C6Q240C8FPGA as a control core，consists of peak detector，A/D conversion，program-controlled amplification，compared shaping and phase-shifting network part.The counter measures the frequency，period and phase of sinusoidal signal.With the equal precision method,the multi-function counter achieves the precise frequency measurement of the sinusoidal signal which its frequency is from1Hz to10MHz，its amplitude is from0.01Vrms to5Vrms，as well as the accurate phase measurement of the sinusoidal signal which its frequency is from10Hz to100kHz，its amplitude is from0.5Vrms to5Vrms.The LCD monitor real-time displays the frequency，period and phase difference of current signal.The multi-function counter features high precision，friendly interface，and strong practical.
上傳時間： 2013-11-15
上傳用戶：gy592333
介紹一種以MSP430單片機為基礎的智能頻率測量系統，采用硬件邏輯與軟件指令相結合的方式控制閘門，實現0 MHz~10 MHz范圍內無檔切換的等精度測量。 Abstract: An intelligent frequency measurement system based on MSP430 singlechip is introduced. The system uses a way that can combine hardware logic and software instructions to contronl the strobe ,and completes the functions of equal precision in the range of 0MHz~10MHz without shifting
上傳時間： 2013-10-28
上傳用戶：dbs012280
The PCA9516 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both the data(SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.The I2C-bus capacitance limit of 400 pF restricts the number ofdevices and bus length. Using the PCA9516 enables the systemdesigner to divide the bus into five segments off of a hub where anysegment to segment transition sees only one repeater delay.
上傳時間： 2013-11-21
上傳用戶：q123321
PCA9511, PCA9512, PCA9513, PCA9514, PCA9515, PCA9516, PCA9518,P82B96, P82B715Abstract - Philips Semiconductors family of Repeaters, Hubs and Expanders are detailed in this application notethat discusses device operation, maximum cable length and frequency calculations and typical applications.
上傳時間： 2013-11-21
上傳用戶：wlcaption
This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
上傳時間： 2013-10-31
上傳用戶：yy_cn
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).
上傳時間： 2013-11-11
上傳用戶：gundamwzc
Tug of War(A tug of war is to be arranged at the local office picnic. For the tug of war, the picnickers must be divided into two teams. Each person must be on one team or the other the number of people on the two teams must not differ by more than 1 the total weight of the people on each team should be as nearly equal as possible. The first line of input contains n the number of people at the picnic. n lines follow. The first line gives the weight of person 1 the second the weight of person 2 and so on. Each weight is an integer between 1 and 450. There are at most 100 people at the picnic. Your output will be a single line containing 2 numbers: the total weight of the people on one team, and the total weight of the people on the other team. If these numbers differ, give the lesser first. )
上傳時間： 2014-01-07
上傳用戶：離殤
