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  • 基于(英蓓特)STM32V100的串口程序

    This example provides a description of how  to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow:    - BaudRate = 115200 baud      - Word Length = 8 Bits    - One Stop Bit    - No parity    - Hardware flow control enabled (RTS and CTS signals)    - Receive and transmit enabled    - USART Clock disabled    - USART CPOL: Clock is active low    - USART CPHA: Data is captured on the second edge     - USART LastBit: The clock pulse of the last data bit is not output to                      the SCLK pin

    標簽: V100 STM 100 32V

    上傳時間: 2013-10-31

    上傳用戶:yy_cn

  • 使用Nios II軟件構建工具

     使用Nios II軟件構建工具 This chapter describes the Nios® II Software Build Tools (SBT), a set of utilities and scripts that creates and builds embedded C/C++ application projects, user library projects, and board support packages (BSPs). The Nios II SBT supports a repeatable, scriptable, and archivable process for creating your software product. You can invoke the Nios II SBT through either of the following user interfaces: ■ The Eclipse™ GUI ■ The Nios II Command Shell The purpose of this chapter is to make you familiar with the internal functionality of the Nios II SBT, independent of the user interface employed.

    標簽: Nios 軟件

    上傳時間: 2013-10-12

    上傳用戶:china97wan

  • Nios II定制指令用戶指南

         Nios II定制指令用戶指南:With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.

    標簽: Nios 定制 指令 用戶

    上傳時間: 2013-10-12

    上傳用戶:kang1923

  • Nios II 系列處理器配置選項

        Nios II 系列處理器配置選項:This chapter describes the Nios® II Processor parameter editor in Qsys and SOPC Builder. The Nios II Processor parameter editor allows you to specify the processor features for a particular Nios II hardware system. This chapter covers the features of the Nios II processor that you can configure with the Nios II Processor parameter editor; it is not a user guide for creating complete Nios II processor systems.

    標簽: Nios II 列處理器

    上傳時間: 2015-01-01

    上傳用戶:mahone

  • XAPP694-從配置PROM讀取用戶數據

    This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configured theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.

    標簽: XAPP PROM 694 讀取

    上傳時間: 2013-10-09

    上傳用戶:guojin_0704

  • XAPP452-Spartan-3高級配置架構

    This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This information can be usedfor partial reconfiguration or partial readback.

    標簽: Spartan XAPP 452 架構

    上傳時間: 2013-11-16

    上傳用戶:qingdou

  • Virtex-6 FPGA PCB設計手冊

    Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.

    標簽: Virtex FPGA PCB 設計手冊

    上傳時間: 2013-11-11

    上傳用戶:zwei41

  • XAPP719 -利用USR_ACCESS寄存器實現PowerPC高速緩存配置

    The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (PPC405) processor caches and/or other data into the FPGA after the FPGAhas been configured, thus achieving partial reconfiguration. The USR_ACCESS_VIRTEX4register is programmed through the bitstream with a command that writes a series of 32-bitwords.

    標簽: USR_ACCESS PowerPC XAPP 719

    上傳時間: 2013-12-23

    上傳用戶:yuanwenjiao

  • XAPP944 - 將Xilinx CoolRunner-II CPLD用作數據流開關

      This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining CPLD resources

    標簽: CoolRunner-II Xilinx XAPP CPLD

    上傳時間: 2013-12-16

    上傳用戶:qwer0574

  • XAPP328-使用CPLD設計MP3播放器

      MP3 portable players are the trend in music-listening technology. These players do not includeany mechanical movements, thereby making them ideal for listening to music during any type ofactivity. MP3 is a digital compression technique based on MPEG Layer 3 which stores music ina lot less space than current CD technology. Software is readily available to create MP3 filesfrom an existing CD, and the user can then download these files into a portable MP3 player tobe enjoyed in almost any environment.

    標簽: XAPP CPLD 328 MP3

    上傳時間: 2013-11-23

    上傳用戶:nanxia

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