fpga design flow from Xilinx
標(biāo)簽： design Xilinx fpga flow
上傳時(shí)間： 2015-12-09
上傳用戶：luopoguixiong
fat file system api in VC
上傳時(shí)間： 2015-12-10
上傳用戶：王慶才
G3傳真的技術(shù)實(shí)現(xiàn)文檔. Digital cellular telecommunications system (Phase 2+) Technical realization of facsimile group 3 transparent. (GSM 03.45 version 8.0.1 Release 1999) ETSI TS 100 931 V8.0.1 (2000-01)
標(biāo)簽： telecommunications realization Technical cellular
上傳時(shí)間： 2014-01-04
上傳用戶：a3318966
IPCAM Design document based on TI DaVinci
標(biāo)簽： document DaVinci Design IPCAM
上傳時(shí)間： 2013-12-26
上傳用戶：songrui
water temperature control system uses the Single Chip Microcomputer to carry on temperature real-time gathering and controling. DS18B20, digitized temperature sensor, provides the temperature signal by "a main line". In -10～+85℃ the scope, DS18B20’s inherent measuring accuracy is 0.5 ℃. The water temperature real-time control system uses the electricity nichrome wire carring on temperature increiseament and operates the electric fan to realize the temperature decrease control. The system has the higher measuring accuracy and the control precision, it also can complete the elevation of temperature and the temperature decrease control.
標(biāo)簽： temperature Microcomputer real-tim control
上傳時(shí)間： 2015-12-10
上傳用戶：nairui21
this the AVR lib who used to design the project for AVR chips
標(biāo)簽： the AVR project design
上傳時(shí)間： 2015-12-10
上傳用戶：jing911003
the operate system used for AVR chips
標(biāo)簽： operate system chips used
上傳時(shí)間： 2015-12-10
上傳用戶：zhaiye
[推薦]彭光紅先生的《小容量單片機(jī)系統(tǒng)的C語言程序結(jié)構(gòu)》Point RTOS monolithic integrated circuit real-time operating system Point RTOS monolithic integrated circuit real-time operating system
標(biāo)簽： monolithic integrated real-time operating
上傳時(shí)間： 2013-12-18
上傳用戶：rocketrevenge
An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.
標(biāo)簽： interconnections approach general include
上傳時(shí)間： 2015-12-12
上傳用戶：lyy1234
MSP430 C 例程_編譯器為IAR embedded workbench,如要更多資料請(qǐng)聯(lián)系我
標(biāo)簽： workbench embedded MSP 430
上傳時(shí)間： 2015-12-13
上傳用戶：comua
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