This temp directory is used by the JVM for temporary file storage. The JVM is configuRed to use this as its java.io.tmpdir in the catalina.sh and catalina.bat scripts.
標(biāo)簽： configuRed JVM directory temporary
上傳時(shí)間： 2016-04-15
上傳用戶：363186
IAR project for MSP430 and uC/OS. All configuRed to start filling with tasks.
標(biāo)簽： configuRed project filling start
上傳時(shí)間： 2014-01-18
上傳用戶：sy_jiadeyi
This example application requires several components to be setup and configuRed before running. It is assumed that you understand how to setup a Web application and add the components below.
標(biāo)簽： application components configuRed requires
上傳時(shí)間： 2016-12-02
上傳用戶：大三三
This program requires the DSP2833x header files. // // As supplied, this project is configuRed for "boot to SARAM" // operation. The 2833x Boot Mode table is shown below. // For information on configuring the boot mode of an eZdsp, // please refer to the documentation included with the eZdsp,
標(biāo)簽： configuRed requires supplied program
上傳時(shí)間： 2014-01-10
上傳用戶：lixinxiang
This application note describes how the NCP3063 can be configuRed as a buck controller to drive an e
標(biāo)簽： 12v 效率 降壓轉(zhuǎn)換器
上傳時(shí)間： 2013-05-28
上傳用戶：mslj2008
Demonstration circuit 1562A is an engineering toolto design and evaluate the LTC699X-X family ofTimerBlox circuits. The center section of the boardcontains a pre-configuRed TimerBlox function.DC1562A comes in twelve timing function variationsas outlined in Table 1.Surrounding the center board is a ”playground”prototyping area. The prototyping area has padsfor Dip-8, S8, MS8, or S6 packages with breadboarding connections to each pin and two convenientpower buses and ground bus surrounding theentire area. This area is for conditioning signals tocontrol the timer function and for adding loads controlled in time.
標(biāo)簽： 6994 LTC PCB 參考設(shè)計(jì)
上傳時(shí)間： 2013-10-18
上傳用戶：如果你也聽說(shuō)
The CAT93C46 is a 1 kb Serial EEPROM memory device which isconfiguRed as either 64 registers of 16 bits (ORG pin at VCC) or 128registers of 8 bits (ORG pin at GND). Each register can be written (orread) serially by using the DI (or DO) pin. The CAT93C46 features aself−timed internal write with auto−clear. On−chip Power−On Resetcircuit protects the internal logic against powering up in the wrongstate.
上傳時(shí)間： 2013-11-20
上傳用戶：ynzfm
This application note describes how to retrieve user-defined data from Xilinx configurationPROMs (XC18V00 and Platform Flash devices) after the same PROM has configuRed theFPGA. The method to add user-defined data to the configuration PROM file is also discussed.The reference design described in this application note can be used in any of the followingXilinx FPGA architectures: Spartan™-II, Spartan-IIE, Spartan-3, Virtex™, Virtex-E, Virtex-II,and Virtex-II Pro.
上傳時(shí)間： 2013-11-11
上傳用戶：zhouli
The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (PPC405) processor caches and/or other data into the FPGA after the FPGAhas been configuRed, thus achieving partial reconfiguration. The USR_ACCESS_VIRTEX4register is programmed through the bitstream with a command that writes a series of 32-bitwords.
標(biāo)簽： USR_ACCESS PowerPC XAPP 719
上傳時(shí)間： 2013-11-13
上傳用戶：我累個(gè)乖乖
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configuRed using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標(biāo)簽： Transceiver Virtex Wizar GTP
上傳時(shí)間： 2013-10-23
上傳用戶：leyesome
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