本軟件是關(guān)于MAX338, MAX339的英文數(shù)據(jù)手冊(cè)：MAX338, MAX339 8通道/雙4通道、低泄漏、CMOS模擬多路復(fù)用器 The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions. These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.
上傳時(shí)間： 2013-11-12
上傳用戶：18711024007
This book is about the digital logic design of microprocessors. It is intended to provide both an understanding of the basic principles of digital logic design, and how these fundamental principles are applied in the building of complex microprocessor circuits using current technologies.
上傳時(shí)間： 2013-10-14
上傳用戶：leyesome
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶：wxqman
MP3 portable players are the trend in music-listening technology. These players do not includeany mechanical movements, thereby making them ideal for listening to music during any type ofactivity. MP3 is a digital compression technique based on MPEG Layer 3 which stores music ina lot less space than current CD technology. Software is readily available to create MP3 filesfrom an existing CD, and the user can then download these files into a portable MP3 player tobe enjoyed in almost any environment.
上傳時(shí)間： 2013-11-23
上傳用戶：nanxia
PCB設(shè)計(jì)問題集錦 問：PCB圖中各種字符往往容易疊加在一起，或者相距很近，當(dāng)板子布得很密時(shí)，情況更加嚴(yán)重。當(dāng)我用Verify Design進(jìn)行檢查時(shí)，會(huì)產(chǎn)生錯(cuò)誤，但這種錯(cuò)誤可以忽略。往往這種錯(cuò)誤很多，有幾百個(gè)，將其他更重要的錯(cuò)誤淹沒了，如何使Verify Design會(huì)略掉這種錯(cuò)誤，或者在眾多的錯(cuò)誤中快速找到重要的錯(cuò)誤。 答：可以在顏色顯示中將文字去掉,不顯示后再檢查;并記錄錯(cuò)誤數(shù)目。但一定要檢查是否真正屬于不需要的文字。 問： What’s mean of below warning:(6230,8330 L1) Latium Rule not checked: COMPONENT U26 component rule.答：這是有關(guān)制造方面的一個(gè)檢查，您沒有相關(guān)設(shè)定，所以可以不檢查。 問： 怎樣導(dǎo)出jop文件？答：應(yīng)該是JOB文件吧？低版本的powerPCB與PADS使用JOB文件。現(xiàn)在只能輸出ASC文件，方法如下STEP：FILE/EXPORT/選擇一個(gè)asc名稱/選擇Select ALL/在Format下選擇合適的版本/在Unit下選Current比較好/點(diǎn)擊OK/完成然后在低版本的powerPCB與PADS產(chǎn)品中Import保存的ASC文件，再保存為JOB文件。 問： 怎樣導(dǎo)入reu文件？答：在ECO與Design 工具盒中都可以進(jìn)行，分別打開ECO與Design 工具盒，點(diǎn)擊右邊第2個(gè)圖標(biāo)就可以。 問： 為什么我在pad stacks中再設(shè)一個(gè)via:1(如附件）和默認(rèn)的standardvi(如附件）在布線時(shí)V選擇1，怎么布線時(shí)按add via不能添加進(jìn)去這是怎么回事，因?yàn)橛袝r(shí)要使用兩種不同的過孔。答：PowerPCB中有多個(gè)VIA時(shí)需要在Design Rule下根據(jù)信號(hào)分別設(shè)置VIA的使用條件，如電源類只能用Standard VIA等等，這樣操作時(shí)就比較方便。詳細(xì)設(shè)置方法在PowerPCB軟件通中有介紹。 問：為什么我把On-line DRC設(shè)置為prevent..移動(dòng)元時(shí)就會(huì)彈出(圖2),而你們教程中也是這樣設(shè)置怎么不會(huì)呢?答：首先這不是錯(cuò)誤,出現(xiàn)的原因是在數(shù)據(jù)中沒有BOARD OUTLINE.您可以設(shè)置一個(gè),但是不使用它作為CAM輸出數(shù)據(jù). 問：我用ctrl+c復(fù)制線時(shí)怎設(shè)置原點(diǎn)進(jìn)行復(fù)制，ctrl+v粘帖時(shí)總是以最下面一點(diǎn)和最左邊那一點(diǎn)為原點(diǎn) 答： 復(fù)制布線時(shí)與上面的MOVE MODE設(shè)置沒有任何關(guān)系,需要在右鍵菜單中選擇,這在PowerPCB軟件通教程中有專門介紹. 問：用(圖4)進(jìn)行修改線時(shí)拉起時(shí)怎總是往左邊拉起(圖5)，不知有什么辦法可以輕易想拉起左就左，右就右。答： 具體條件不明,請(qǐng)檢查一下您的DESIGN GRID,是否太大了. 問： 好不容易拉起右邊但是用(圖6)修改線怎么改怎么下面都會(huì)有一條不能和在一起，而你教程里都會(huì)好好的(圖8)答：這可能還是與您的GRID 設(shè)置有關(guān),不過沒有問題,您可以將不需要的那段線刪除.最重要的是需要找到布線的感覺,每個(gè)軟件都不相同,所以需要多練習(xí)。 問： 尊敬的老師:您好！這個(gè)圖已經(jīng)畫好了，但我只對(duì)（如圖1）一種的完全間距進(jìn)行檢查，怎么錯(cuò)誤就那么多，不知怎么改進(jìn)。請(qǐng)老師指點(diǎn)。這個(gè)圖在附件中請(qǐng)老師幫看一下，如果還有什么問題請(qǐng)指出來，本人在改進(jìn)。謝！！！！！答：請(qǐng)注意您的DRC SETUP窗口下的設(shè)置是錯(cuò)誤的,現(xiàn)在選中的SAME NET是對(duì)相同NET進(jìn)行檢查,應(yīng)該選擇NET TO ALL.而不是SAME NET有關(guān)各項(xiàng)參數(shù)的含義請(qǐng)仔細(xì)閱讀第5部教程. 問： U101元件已建好，但元件框的拐角處不知是否正確，請(qǐng)幫忙CHECK 答：元件框等可以通過修改編輯來完成。問： U102和U103元件沒建完全，在自動(dòng)建元件參數(shù)中有幾個(gè)不明白：如：SOIC--》silk screen欄下spacing from pin與outdent from first pin對(duì)應(yīng)U102和U103元件應(yīng)寫什么數(shù)值，還有這兩個(gè)元件SILK怎么自動(dòng)設(shè)置，以及SILK內(nèi)有個(gè)圓圈怎么才能畫得與該元件參數(shù)一致。 答：Spacing from pin指從PIN到SILK的Y方向的距離,outdent from first pin是第一PIN與SILK端點(diǎn)間的距離.請(qǐng)根據(jù)元件資料自己計(jì)算。
標(biāo)簽： PCB 設(shè)計(jì)問題 集錦
上傳時(shí)間： 2014-01-03
上傳用戶：Divine
|Introduction Basic Concept Tips to layout Power circuit Type of Power circuit Basic Concept Maximum Current calculation Resistance of Copper ideal power supply & noise Capacitor & Inductor Power consumption Function of power circuit
標(biāo)簽： PCB 電源設(shè)計(jì)
上傳時(shí)間： 2013-12-10
上傳用戶：JIEWENYU
Current design flow challenges
標(biāo)簽： Cosimulation_with_layout ADS 原理圖 版圖
上傳時(shí)間： 2013-11-06
上傳用戶：jiangxiansheng
超導(dǎo)限流器作為非線性元件短路電流限制器，具有體積小、重量輕、損耗小的特點(diǎn)。飽和鐵心型超導(dǎo)限流器（Saturated Iron Core Superconductive Fault Current Limiter--SICSFCL）作為超導(dǎo)限流器中具有技術(shù)優(yōu)勢(shì)，可適用于高壓電網(wǎng)的限流器必將得到廣泛應(yīng)用，本文通過對(duì)SICSFCL工作原理分析，運(yùn)用Ansoft軟件搭建220 kV/800A型號(hào)的SICSFCL，分析其不同外部短路電流下工作特性。表明SICSFCL對(duì)于220 kV電網(wǎng)短路電流具有良好的限制作用，可滿足電網(wǎng)中電氣設(shè)備的安全可靠運(yùn)行要求。
標(biāo)簽： SICSFCL Ansoft 220 kV
上傳時(shí)間： 2013-11-12
上傳用戶：xiaohanhaowei
為了提高直接轉(zhuǎn)矩控制（DTC）系統(tǒng)定子磁鏈估計(jì)精度，降低電流、電壓測(cè)量的隨機(jī)誤差，提出了一種基于擴(kuò)展卡爾曼濾波（EKF）實(shí)現(xiàn)異步電機(jī)轉(zhuǎn)子位置和速度估計(jì)的方法。擴(kuò)展卡爾曼濾波器是建立在基于旋轉(zhuǎn)坐標(biāo)系下由定子電流、電壓、轉(zhuǎn)子轉(zhuǎn)速和其它電機(jī)參量所構(gòu)成的電機(jī)模型上，將定子電流、定子磁鏈、轉(zhuǎn)速和轉(zhuǎn)子角位置作為狀態(tài)變量，定子電壓為輸入變量，定子電流為輸出變量，通過對(duì)磁鏈和轉(zhuǎn)速的閉環(huán)控制提高定子磁鏈的估計(jì)精度，實(shí)現(xiàn)了異步電機(jī)的無速度傳感器直接轉(zhuǎn)矩控制策略，仿真結(jié)果驗(yàn)證了該方法的可行性,提高了直接轉(zhuǎn)矩的控制性能。 Abstract: In order to improve the Direct Torque Control（DTC） system of stator flux estimation accuracy and reduce the current， voltage measurement of random error， a novel method to estimate the speed and rotor position of asynchronous motor based on extended Kalman filter was introduced. EKF was based on d-p axis motor and other motor parameters （state vector: stator current， stator flux linkage， rotor angular speed and position； input: stator voltage； output: staror current). EKF was designed for stator flux and rotor speed estimation in close-loop control. It can improve the estimated accuracy of stator flux. It is possible to estimate the speed and rotor position and implement asynchronous motor drives without position and speed sensors. The simulation results show it is efficient and improves the control performance.
標(biāo)簽： EKF 異步電機(jī) 直接轉(zhuǎn)矩 控制系統(tǒng)
上傳時(shí)間： 2015-01-02
上傳用戶：qingdou
西門子建筑電器-電氣安裝技術(shù)部發(fā)行的各類產(chǎn)品樣本：小型斷路器、剩余電流保護(hù)斷路器和模數(shù)化產(chǎn)品(中/ 英文)Miniature Circuit-Breakers, Residual Current Operated Circuit-Breakers and Modular Devices (Chinese/English)低壓熔斷器系統(tǒng)(中/ 英文)Fuse System (Chinese/English)雷擊，過電壓－不再是問題(中文)Thunderstorms - no problem (Chinese)西門子建筑電器目錄(中文)Electrical Installation Technology Catalog (Chinese)終端配電保護(hù)產(chǎn)品(中文)5 IN 1 (Chinese)SIKUS 和 STAB UNIVERSAL 目錄(中文)SIKUS and STAB UNIVERSAL Catalogue (Chinese)SIKUS HC 目錄(中文)SIKUS HC Catalogue (Chinese)SentronTM 母線槽 (中文)SentronTM Busway System (Chinese)SentronTM 母線槽系統(tǒng)快速選型 (準(zhǔn)備中) (中文)SentronTM Busway System quick selection (in preparing) (Chinese)建筑低壓配電一體化解決方案－住宅小區(qū)應(yīng)用(中文)Building LV PD Solution (Chinese)西門子 DELTA vista“遠(yuǎn)景”系列開關(guān)和插座價(jià)目表(中文)Delta vista Switch and Socket Pricelist (Chinese)instabus EIB 面向未來的樓宇智能控制系統(tǒng)(中文)instabus EIB (Chinese)instabus EIB 面向未來的樓宇智能控制系統(tǒng)技術(shù)手冊(cè) (準(zhǔn)備中) (中文)instabus EIB technical handbook (in preparing) (Chinese)西門子電氣安裝技術(shù)業(yè)績卓越(中/ 英文)ET Reference Manual (Chinese/English)
上傳時(shí)間： 2013-11-23
上傳用戶：瓦力瓦力hong
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