The PCA9537 is a 10-pin CMOS device that provides 4 bits of General Purpose parallelInput/Output (GPIO) expansion with interrupt and reset for I2C-bus/SMBus applicationsand was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders.I/O expanders provide a simple solution when additional I/O is needed for ACPI powerswitches, sensors, push-buttons, LEDs, fans, etc.
上傳時間： 2013-10-14
上傳用戶：wuchunzhong
The PCA9538 is a 16-pin CMOS device that provides 8 bits of General Purpose parallelInput/Output (GPIO) expansion with interrupt and reset for I2C-bus/SMBus applicationsand was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders.I/O expanders provide a simple solution when additional I/O is needed for ACPI powerswitches, sensors, push-buttons, LEDs, fans, etc.
上傳時間： 2014-01-24
上傳用戶：youmo81
The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed toenhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvementsinclude higher drive capability, 5 V I/O tolerance, lower supply current, individual I/Oconfiguration, and smaller packaging. I/O expanders provide a simple solution whenadditional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Outputand Polarity Inversion (active HIGH or active LOW operation) registers. The systemmaster can enable the I/Os as either inputs or outputs by writing to the I/O configurationbits. The data for each Input or Output is kept in the corresponding Input or Outputregister. The polarity of the read register can be inverted with the Polarity Inversionregister. All registers can be read by the system master. Although pin-to-pin and I2C-busaddress compatible with the PCF8575, software changes are required due to theenhancements, and are discussed in Application Note AN469.
上傳時間： 2013-11-13
上傳用戶：fredguo
The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption and a high-impedance open-drain output pin, IO0. The system master can enable the PCA9557’s I/O as either input or output by writing to the configuration register. The system master can also invert the PCA9557 inputs by writing to the active HIGH polarity inversion register. Finally, the system master can reset the PCA9557 in the event of a time-out by asserting a LOW in the reset input. The power-on reset puts the registers in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part.
上傳時間： 2014-01-18
上傳用戶：bs2005
The CAT9555 is a CMOS device that provides 16-bitparallel input/output port expansion for I²C and SMBuscompatible applications. These I/O expanders providea simple solution in applications where additional I/Osare needed: sensors, power switches, LEDs,pushbuttons, and fans.
上傳時間： 2014-01-09
上傳用戶：1101055045
The CAT9534 is an 8-bit parallel input/output portexpander for I²C and SMBus compatible applications.These I/O expanders provide a simple solution inapplications where additional I/Os are needed: sensors,power switches, LEDs, pushbuttons, and fans.The CAT9534 consists of an input port register, anoutput port register, a configuration register, a polarityinversion register and an I²C/SMBus-compatible serialinterface.
上傳時間： 2013-11-09
上傳用戶：liulinshan2010
Designing Boards with Atmel AT89C51, AT89C52, AT89C1051, and AT89C2051 for Writing Flash at In-Circuit Test:Recent improvements in chips andtesters have made it possible for thetester to begin taking over the role traditionallyassigned to the PROM programmer.Instead of having a PROM programmerwrite nonvolatile memoriesbefore assembling the board, the in-circuittester writes them during in-circuittesting operations. Many Teradyne Z18-series testers are now in use loadingcode into nonvolatile memories, microcontrollersand in-circuit programmable logic devices. The purpose of this note is to explain how the Z18 approaches the writing task for Atmel AT89C series IC’s,so that designers of boards using these chips can get the best results.
標簽： Designing Boards Atmel with
上傳時間： 2013-11-20
上傳用戶：lijianyu172
The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using SW routines implemented in C. The code is focused onthe SAB C513, but will fit to all C500 derivatives.Beyond the low level software drivers a test shell is delivered. This shell allows a quicktest of the software drivers by an emulator or a starter kit demo board.
上傳時間： 2013-11-24
上傳用戶：363186
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上傳時間： 2013-10-23
上傳用戶：copu
Abstract: This application note explains the hardware of different types of 1-Wire® interfaces and software examples adapted to this hardware with a focus on serial ports. Depending on the types of iButtons required for a project and the type of computer to be used, the most economical interface is easily found. The hardware examples shown are basically two different types: 5V general interface and 12V RS-232 interface. Within the 5V group a common printed circuit board could be used for all circuits described. The variations can be achieved by different populations of components. The same principal is used for the 12V RS-232 interface. The population determines if it is a Read all or a Read/Write all type of interface. There are other possible circuit implementations to create a 1-Wire interface. The circuits described in this application note cover many different configurations. For a custom application, one of the described options can be adapted to meet individual needs.
標簽： iButtons Reading Writing and
上傳時間： 2013-10-29
上傳用戶：long14578
