1 /**————————————————————2 〖說明〗I2C總線驅(qū)動(dòng)程序(用兩個(gè)普通IO模擬I2C總線)3 包括100Khz(T=10us)的標(biāo)準(zhǔn)模式(慢速模式)選擇，4 和400Khz(T=2.5us)的快速模式選擇，5 默認(rèn)11.0592Mhz的晶振。6 〖文件〗PCF8563T.C ﹫2001/11/2 77 〖作者〗龍嘯九天 c51@yeah.net http://www.c51bbs.co /8 〖修改〗修改建議請到論壇公布 http://www.c51bbs.co m9 〖版本〗V1.00A Build 080310 —————————————————————*/1112 #ifndef SDA13 #define SDA P0_014 #define SCL P0_115 #endif1617 extern uchar SystemError;1819 #define uchar unsigned char20 #define uint unsigned int21 #define Byte unsigned char22 #define Word unsigned int23 #define bool bit24 #define true 125 #define false 02627 #define SomeNOP(); _nop_();_nop_();_nop_();_nop_();2829 /**--------------------------------------------------------------------------------30 調(diào)用方式：void I2CStart(void) ﹫2001/07/0 431 函數(shù)說明：私有函數(shù)，I2C專用32 ---------------------------------------------------------------------------------*/33 void I2CStart(void)34 {35 EA=0;36 SDA=1; SCL=1; SomeNOP();//INI37 SDA=0; SomeNOP(); //START38 SCL=0;39 }4041 /**--------------------------------------------------------------------------------42 調(diào)用方式：void I2CStop(void) ﹫2001/07/0 443 函數(shù)說明：私有函數(shù)，I2C專用44 ---------------------------------------------------------------------------------*/45 void I2CStop(void)46 {47 SCL=0; SDA=0; SomeNOP(); //INI48 SCL=1; SomeNOP(); SDA=1; //STOP49 EA=1;50 }5152 /**--------------------------------------------------------------------------------53 調(diào)用方式：bit I2CAck(void) ﹫2001/07/0 454 函數(shù)說明：私有函數(shù)，I2C專用，等待從器件接收方的應(yīng)答55 ---------------------------------------------------------------------------------*/56 bool WaitAck(void)57 {58 uchar errtime=255;//因故障接收方無ACK，超時(shí)值為255。59 SDA=1;SomeNOP();60 SCL=1;SomeNOP();61 while(SDA) {errtime--; if (!errtime) {I2CStop();SystemError=0x11;return false;}}62 SCL=0;63 return true;
標(biāo)簽： I2C 總線 驅(qū)動(dòng)程序
上傳時(shí)間： 2014-04-11
上傳用戶：xg262122
摘 要: 針對三峽水輪機(jī)葉片坑內(nèi)移動(dòng)式修焊機(jī)器人的作業(yè)過程測控問題, 研制了一種基于雙數(shù)字信號(hào)處理器的嵌入式視覺反饋控制系統(tǒng)。 采用功能單元模塊化設(shè)計(jì)思想和疊層積木式裝配結(jié)構(gòu), 該系統(tǒng)將基于TM S320DM 642 的圖像采集與處理、 基于TM S320L F2812 的運(yùn)動(dòng)控制與參數(shù)調(diào)整、 數(shù)字視頻輸入、 模擬視頻輸入、 模擬視頻輸出、 數(shù)字視頻輸出、 電源變換等功能模塊集成在170mm×57mm×40mm 的空間尺寸內(nèi)。該系統(tǒng)可以安裝在移動(dòng)式修復(fù)機(jī)器人上、 脫離工控機(jī)獨(dú)立工作, 適用于M IG、T IG、CO 2 等多種焊接工藝方法的過程監(jiān)控、 焊縫跟蹤和焊縫成形實(shí)時(shí)控制。 關(guān)鍵詞: 移動(dòng)式修焊機(jī)器人; 雙數(shù)字信號(hào)處理器嵌入式系統(tǒng); 視覺反饋控制
標(biāo)簽： DSP 移動(dòng) 焊 機(jī)器人
上傳時(shí)間： 2013-10-08
上傳用戶：xinhaoshan2016
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the VSIA Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.
上傳時(shí)間： 2014-01-24
上傳用戶：xinhaoshan2016
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標(biāo)簽： Transceiver Virtex Wizar GTP
上傳時(shí)間： 2013-10-23
上傳用戶：leyesome
提出一種融合Ad hoc網(wǎng)絡(luò)、GPRS/GSM和PSTN的遠(yuǎn)程分布式環(huán)境狀況實(shí)時(shí)監(jiān)測系統(tǒng)設(shè)計(jì)方案。由IEEE 802.15.4標(biāo)準(zhǔn)組建的Ad hoc無線傳感器網(wǎng)絡(luò)負(fù)責(zé)監(jiān)測環(huán)境溫濕度、光照度、煤氣及CO濃度等；采用GPRS/GSM模塊和嵌入式Modem構(gòu)造無線網(wǎng)關(guān)，實(shí)現(xiàn)Ad hoc網(wǎng)絡(luò)與GPRS/GSM和PSTN的無縫連接，將無線傳感器網(wǎng)絡(luò)采集的數(shù)據(jù)發(fā)送到手機(jī)或遠(yuǎn)端計(jì)算機(jī)。系統(tǒng)具有小、遠(yuǎn)和散的特點(diǎn)，可實(shí)現(xiàn)多點(diǎn)分布、中央管理、多層報(bào)警和遠(yuǎn)程監(jiān)測。
標(biāo)簽： 多網(wǎng)融合 環(huán)境 實(shí)時(shí)監(jiān)測 遠(yuǎn)程
上傳時(shí)間： 2013-11-08
上傳用戶：semi1981
致力于提供高速信號(hào)處理解決方案的北京拓目科技有限公司（Beijing Topmoo Tech Co. Ltd）在2011年推出基于FLASH陣列存儲(chǔ)的高端固態(tài)存儲(chǔ)產(chǎn)品TMS-F231-160G之后，近日宣布推出其入門級(jí)固態(tài)存儲(chǔ)產(chǎn)品TMS-S231-512G。 在容量選擇上，TMS-F231-160G可以通過更換PIN2PIN的FLASH芯片而達(dá)到擴(kuò)容目的,但是SLC FLASH成本高居不下，在目前高速發(fā)展的工業(yè)相機(jī)領(lǐng)域，難以推廣普及。為了推動(dòng)高速工業(yè)相機(jī)存儲(chǔ)市場的發(fā)展，拓目科技發(fā)布了基于SATA接口的SSD盤存儲(chǔ)系統(tǒng)TMS-S231-512G，隨著消費(fèi)電子的發(fā)展，SSD的單盤容量不斷的擴(kuò)大，價(jià)格不斷的降低，必然能使TMS-S231-512G得到廣泛的應(yīng)用。 “TMS-S231-512G是一款專門針對航空拍攝、工業(yè)照相、汽車碰撞實(shí)驗(yàn)等需要高速圖像采集、存儲(chǔ)的場合而開發(fā)的固態(tài)存儲(chǔ)設(shè)備”拓目科技產(chǎn)品經(jīng)理Lemon Chan介紹道，“該產(chǎn)品的單盤存儲(chǔ)容量最高可達(dá)512GB，單盤存儲(chǔ)帶寬則最高可達(dá)250MB/s，在該帶寬支持條件下，TMS-S231-512G最高能支持1280x1024@200fps的連續(xù)拍照模式，幾乎適用于所有需要高速圖像采集的場合”。 “目前，Camera Link接口在航空相機(jī)、工業(yè)相機(jī)等領(lǐng)域得到廣泛應(yīng)用。與此同時(shí)，TMS-S231-512G板載兩個(gè)SFP光纖接口，最高可支持5Gbps的有效數(shù)據(jù)吞吐率。”拓目科技研發(fā)總監(jiān)Steven Wu介紹道，“除了硬件板卡以外，拓目科技還提供一整套完整的客戶端解決方案，以方便客戶能夠輕易地對設(shè)備進(jìn)行管控，同時(shí)方便客戶對記錄下來的數(shù)據(jù)進(jìn)行預(yù)覽、下載等操作”。 “與國外同類產(chǎn)品相比，TMS-S231-512G除了大容量、高帶寬等優(yōu)點(diǎn)以外，另一大優(yōu)勢在于其極強(qiáng)的可定制性。TMS-S231-512G從硬件設(shè)計(jì)到軟件開發(fā)，所有的核心技術(shù)都由拓目科技研發(fā)團(tuán)隊(duì)自主開發(fā)，相比于國外同類產(chǎn)品，拓目科技無論在產(chǎn)品的可定制性還是售后技術(shù)支持方面，都具有較大的優(yōu)勢”Steven Wu補(bǔ)充道。 同時(shí)，該款產(chǎn)品所有器件均采用工業(yè)級(jí)寬溫芯片，溫度、振動(dòng)等環(huán)境適應(yīng)性試驗(yàn)均已順利通過，能最大程度地保證產(chǎn)品在惡劣環(huán)境下的可靠性。 TMS-S231系列產(chǎn)品特點(diǎn) 1， 采用業(yè)界領(lǐng)先的掉電保護(hù)技術(shù)，令您的數(shù)據(jù)安全無憂 2， 性能卓越，擁有單盤高達(dá)250MB/s的寫帶寬 3， 單盤64GB~512GB大容量可選，存儲(chǔ)容量大小也可以根據(jù)用戶需求定制 4， 支持Camera Link視頻輸入接口 5， 支持DVI顯示接口 6， 支持SFP光纖接口 7， 支持2個(gè)SSD盤 8， 支持1個(gè)千兆以太網(wǎng)口 9， 滿足各種惡劣環(huán)境應(yīng)用要求，能在高溫度、多灰塵、高海拔、強(qiáng)振動(dòng)等應(yīng)用場合下正常使用 TMS-S231采用12V電源適配器供電，功耗小于10W，TMS-S231集成度非常高，產(chǎn)品體積僅為260mm x 180mm x 45mm，如上圖所示。TMS-S231現(xiàn)已進(jìn)入大批量生產(chǎn)階段并隨時(shí)接受客戶試用申請與訂貨。
上傳時(shí)間： 2013-11-12
上傳用戶：a155166
The main objective of this book is to present all the relevant informationrequired for RF and micro-wave power amplifier design includingwell-known and novel theoretical approaches and practical design techniquesas well as to suggest optimum design approaches effectively combininganalytical calculations and computer-aided design. This bookcan also be very useful for lecturing to promote the analytical way ofthinking with practical verification by making a bridge between theoryand practice of RF and microwave engineering. As it often happens, anew result is the well-forgotten old one. Therefore, the demonstrationof not only new results based on new technologies or circuit schematicsis given, but some sufficiently old ideas or approaches are also introduced,that could be very useful in modern practice or could contributeto appearance of new ideas or schematic techniques.
標(biāo)簽： Amplifier Microwave Design Power
上傳時(shí)間： 2013-12-22
上傳用戶：vodssv
采用60 Co 作為輻射源模擬空間輻射環(huán)境, 對光纖陀螺及其光電器件進(jìn)行了大量的試驗(yàn), 并對光纖陀螺及其光電器件受空間輻射影響的機(jī)理進(jìn)行了研究, 得出光纖陀螺光電器件中保偏光纖環(huán)受輻射影響最嚴(yán) 重, 從而重點(diǎn)分析了光纖陀螺敏感器件保偏光纖環(huán)的輻射影響機(jī)理, 從原理上探討了保偏光纖環(huán)在輻射條件下?lián)p耗的增加對光纖陀螺的影響, 為光纖陀螺抗輻射加固技術(shù)提供了理論基礎(chǔ)。
上傳時(shí)間： 2013-10-08
上傳用戶：pei5
解壓密碼：www.elecfans.com 隨著微電子技術(shù)的迅速發(fā)展以及集成電路規(guī)模不斷提高，對電路性能的設(shè)計(jì) 要求越來越嚴(yán)格，這勢必對用于大規(guī)模集成電路設(shè)計(jì)的EDA 工具提出越來越高的 要求。自1972 年美國加利福尼亞大學(xué)柏克萊分校電機(jī)工程和計(jì)算機(jī)科學(xué)系開發(fā) 的用于集成電路性能分析的電路模擬程序SPICE（Simulation Program with IC Emphasis）誕生以來，為適應(yīng)現(xiàn)代微電子工業(yè)的發(fā)展，各種用于集成電路設(shè)計(jì)的 電路模擬分析工具不斷涌現(xiàn)。HSPICE 是Meta-Software 公司為集成電路設(shè)計(jì)中 的穩(wěn)態(tài)分析，瞬態(tài)分析和頻域分析等電路性能的模擬分析而開發(fā)的一個(gè)商業(yè)化通 用電路模擬程序，它在柏克萊的SPICE（1972 年推出），MicroSim公司的PSPICE （1984 年推出）以及其它電路分析軟件的基礎(chǔ)上，又加入了一些新的功能，經(jīng) 過不斷的改進(jìn)，目前已被許多公司、大學(xué)和研究開發(fā)機(jī)構(gòu)廣泛應(yīng)用。HSPICE 可 與許多主要的EDA 設(shè)計(jì)工具，諸如Candence,Workview 等兼容，能提供許多重要 的針對集成電路性能的電路仿真和設(shè)計(jì)結(jié)果。采用HSPICE 軟件可以在直流到高 于100MHz 的微波頻率范圍內(nèi)對電路作精確的仿真、分析和優(yōu)化。在實(shí)際應(yīng)用中， HSPICE能提供關(guān)鍵性的電路模擬和設(shè)計(jì)方案，并且應(yīng)用HSPICE進(jìn)行電路模擬時(shí)， 其電路規(guī)模僅取決于用戶計(jì)算機(jī)的實(shí)際存儲(chǔ)器容量。 The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In addition, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming interfaces (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.
標(biāo)簽： download hspice 2007
上傳時(shí)間： 2013-11-10
上傳用戶：123312
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