Avalon_VGA，-- This design provides an interface to the Alcahest VGA daughter card. -- The design comprises of an 8-bit VGA driver with Avalon bus interfaces. There are a total of -- three Avalon interfaces.
標簽： Avalon_VGA
上傳時間： 2015-07-07
上傳用戶：kikye
Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model
標簽： Algorithm Decoder DVB-RCS Release
上傳時間： 2015-07-10
上傳用戶：清風冷雨
Turbo C - (C) Copyright 1987, 1988 by Borland International */ #define S_IREAD 0x0100 /* from SYS\STAT.H */ #define S_IWRITE 0x0080 /* from SYS\STAT.H */ #define TRUE 1 #define FALSE 0 #define MSGHEADER "MICROCALC - A Turbo C Demonstration Program" #define MSGKEYPRESS "Press any key to continue." #define MSGCOMMAND "Press / for the list of commands" #define MSGMEMORY "Memory Available:" #define MSGERROR "ERROR" 部分說明 #define MSGLOMEM "Not enough memory to allocate cell." #define MSGEMPTY "Empty" #define MSGTEXT "Text"
標簽： International Copyright Borland S_IREAD
上傳時間： 2013-12-26
上傳用戶：llandlu
#define MSGHEADER "MICROCALC - A Turbo C Demonstration Program" #define MSGKEYPRESS "Press any key to continue." #define MSGCOMMAND "Press / for the list of commands" #define MSGMEMORY "Memory Available:" #define MSGERROR "ERROR" #define MSGLOMEM "Not enough memory to allocate cell."
標簽： define Demonstration MSGKEYPRESS MSGHEADER
上傳時間： 2015-07-22
上傳用戶：xinzhch
Blind Equalizer 的演算法主要是利用CMA及 LMS 的配合，當CMA將EYE打開，使訊號趨近于正確值，就切換到LMS，利用Slicer的輸出當作training sequence來調整Equalizer的系數，而Carrier Recovery 的部份，則是將phase error track出來
上傳時間： 2013-12-28
上傳用戶：it男一枚
關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
串口通訊使用說明 在兩臺機器運行serealcom.exe， 但必須保證用串口線連接， 選擇串口時如出現error, 表明此串口正被其它設備使用。
上傳時間： 2014-10-12
上傳用戶：洛木卓
// // BEZIER.RC2 - resources Microsoft Visual C++ does not edit directly // #ifdef APSTUDIO_INVOKED #error this file is not editable by Microsoft Visual C++ #endif //APSTUDIO_INVOKED
標簽： APSTUDIO_INV Microsoft resources directly
上傳時間： 2015-08-05
上傳用戶：han_zh
查找線性表中的某元素：L為帶頭接點的單鏈表的頭指針，當第i個元素存在的時候，其值賦給e并返回OK,否則返回ERROR */
上傳時間： 2013-12-14
上傳用戶：363186
The objective of this projectis to design, model and simulate an autocorrelation generator circuit using 4-bit LFSR. the register and LFSR will used D flip-flop and some gates. By the autocorrelation concept, there should be 2 same length vectors, for calculating the autocorrelation , we have to design the register for storing the original vector and the shifter for make time delay.
標簽： autocorrelation objective generator projectis
上傳時間： 2015-08-17
上傳用戶：ikemada
