This paper reviews key factors to practical ESD protection design for RF and analog/mixed-signal (AMS) ICs, including general challenges emerging, ESD-RFIC interactions, RF ESD design optimization and prediction, RF ESD design characterization, ESD-RFIC co-design technique, etc. Practical design examples are discussed. It means to provide a systematic and practical design flow for whole-chip ESD protection design optimization and prediction for RF/AMS ICs to ensure 1 st Si design success.
標(biāo)簽： ESD_protection_for_RF_and_AMS_ICs
上傳時間： 2020-06-05
上傳用戶：shancjb
The “bottom-line” metrics of cash flow, demand, price, and return on investment are driven by a second set of financial metrics represented by value to the customer, cost, and the pace of innovation. Get them right relative to competition and impressive bottom-line results should follow. Because of their importance, we call value to the customer, variable cost, and the pace of innovation the “fundamental metrics.”
標(biāo)簽： Planning Product Systems Driven Value and
上傳時間： 2020-06-06
上傳用戶：shancjb
Control systems are used to regulate an enormous variety of machines, products, and processes. They control quantities such as motion, temperature, heat flow, fluid flow, fluid pressure, tension, voltage, and current. Most concepts in control theory are based on having sensors to measure the quantity under control. In fact, control theory is often taught assuming the availability of near-perfect feedback signals. Unfortunately, such an assumption is often invalid. Physical sensors have shortcomings that can degrade a control system.
標(biāo)簽： Observers Control Systems in
上傳時間： 2020-06-10
上傳用戶：shancjb
華為敏捷園區(qū)解決方案終端安全技術(shù)白皮書(Forescout)1 用戶準(zhǔn)入檢查，保證身份合法： 在用戶訪問網(wǎng)絡(luò)訪問之前驗證用戶的身份，只有合法的用戶才允許接入網(wǎng)絡(luò)。這就是 基于用戶身份的準(zhǔn)入機(jī)制，包括 802.1x,Portal,MAC bypass 這幾種典型的認(rèn)證方式。 準(zhǔn)入檢查由客戶端+網(wǎng)絡(luò)設(shè)備+AAA 服務(wù)器組成。在 Agile Campus 解決方案中，AAA 服務(wù)器可以使用自研的 Agile Controller-Campus 1.0，也可以與第三方 Server 對接，例 如 Cisco ISE 系統(tǒng)。 2 終端合規(guī)性檢查，保證終端合規(guī)： 檢查用戶使用的終端是否符合企業(yè)制定的安全策略，例如防病毒和操作系統(tǒng)補(bǔ)丁策 略。可疑或有問題的主機(jī)將被隔離或限制網(wǎng)絡(luò)接入范圍，直到它經(jīng)過修補(bǔ)或采取了相 應(yīng)的安全措施為止。 終端合規(guī)檢查由客戶端+服務(wù)器組成，該系統(tǒng)可以獨立部署。若需要將合規(guī)檢查結(jié)果作 為 NAC 控制條件，AAA 系統(tǒng)必須與終端合規(guī)檢查服務(wù)器實現(xiàn)聯(lián)動。 在 Agile Campus 解決方案中，終端合規(guī)檢查采用集成第三方廠家方式實現(xiàn)。 3 業(yè)務(wù)隨行，保證用戶業(yè)務(wù)一致性體驗 基于安全組的策略規(guī)劃，實現(xiàn)全網(wǎng)策略的統(tǒng)一部署與自動同步，確保全網(wǎng)策略一致， 讓用戶自由移動時享受一致的業(yè)務(wù)體驗。 業(yè)務(wù)隨行由網(wǎng)絡(luò)設(shè)備+AAA 服務(wù)器+策略服務(wù)器組成。在 Agile Campus 解決方案中，若 客戶希望同時部署終端合規(guī)檢查和業(yè)務(wù)隨行，需要部署 Agile Controller-Campus 1.0， 同時集成合規(guī)檢查服務(wù)器。
標(biāo)簽： 華為敏捷園區(qū)
上傳時間： 2022-02-28
上傳用戶：
針對嵌入式產(chǎn)品程序更新問題,提出了一種基于IAP技術(shù)的STM32單片機(jī)在線固件升級方案,設(shè)計了STM32單片機(jī)最小系統(tǒng)硬件電路和USB轉(zhuǎn)串口通信電路,并給出了Bootloader程序、APP程序、PC上機(jī)程序的實現(xiàn)流程.實驗結(jié)果表明,該方案具有簡單實用、穩(wěn)定性高、維護(hù)成本低和設(shè)備使用效率高的特點,適用于嵌入式產(chǎn)品升級.For the problem of updating embedded products program,an online firmware upgrade scheme of STM32 single chip microcomputer based on IAP technology is proposed.This scheme not only elaborates the principle of IAP technology in detail but also provides the design of the minimum system hardware circuit of STM32 MCU,the design of USB for serial communication circuit,and the implementation flow of Bootloader program,APP program and PC program.The experiment results show that the scheme is simple,practical and highly stable.In addition,it can be used to actual embedded product upgrading,significantly reducing maintenance costs and improving the efficiency of equipment.
上傳時間： 2022-03-25
上傳用戶：
在全球氣候變暖和石油資源短缺的形勢下,推動新能源汽車的發(fā)展將成為汽車行業(yè)一種新的發(fā)展方向。在大力發(fā)展新能源電動汽車行業(yè)的同時還應(yīng)兼顧電動汽車充電設(shè)施的發(fā)展,因此對電動汽車充電樁的設(shè)計與研究顯得十分必要。對電動汽車直流充電樁的硬件系統(tǒng)進(jìn)行設(shè)計,主要的硬件電路包括安全監(jiān)測電路、總壓采集電路、溫濕度檢測電路、語音電路。軟件包括主要流程圖和溫濕度檢測流程圖。Under the situation of global warming and shortage of petroleum resources,promoting the development of new energy vehicles will become a new development direction for the automotive industry.While vigorously developing the new energy electric vehicle industry,we should also take into account the development of electric vehicle charging facilities.Therefore,the design and research of electric vehicle charging piles is very necessary.The hardware system of the electric vehicle DC charging pile is designed.The main hardware circuits include safety monitoring circuit,total voltage collecting circuit,temperature and humidity detecting circuit,voice circuit and CAN communication.The software includes a main flow chart and a temperature and humidity detection flow chart.
標(biāo)簽： 電動汽車
上傳時間： 2022-04-03
上傳用戶：jason_vip1
基于TMS320F28335的超聲波流量計硬件原理圖+軟件源碼本文以TMS320F28335 處理器為核心，設(shè)計一種用于管道流量測量的超聲波流量計。系統(tǒng)硬件由核心板，超聲波發(fā)射和接收電路，切換電路，超聲換能器，基于ADS805 的高速信號采集電路，人機(jī)交互以及電源等模塊構(gòu)成。采用時差法進(jìn)行管道流量測量，時差測量采用SCOT 加權(quán)的廣義互相關(guān)時延估計算法。本論文設(shè)計的超聲波流量計具有測量速度快、準(zhǔn)確性好、成本低等優(yōu)點。關(guān)鍵字：C2000，超聲波，流量，廣義互相關(guān)算法AbstractA kind of ultrasonic flowmeter using for the pipe flow measurement is designed based onTMS320F28335 in this paper. The system hardware consists of the following parts: the core board,ultrasonic signal transmitter and receiver circuits, switch circuit, ultrasonic transducer, signalacquisition circuit based on ADS805, human-computer interaction module and power supplymodule, etc. The system use the method of time difference for pipeline flow measurement and thetime difference is calculated by the time-delay algorithm of SCOT weighted generalizedcross-correlation. The ultrasonic flowmeter has the features of high testing speed, high precisionand low cost, etc.Keywords: C2000,Ultrasonic, Flow, Generalized Cross-Correlation Algorithm
標(biāo)簽： tms320f28335 超聲波流量計
上傳時間： 2022-05-06
上傳用戶：
Vivado設(shè)計分為Project Mode和Non-project Mode兩種模式，一般簡單設(shè)計中，我們常用的是Project Mode。在本手冊中，我們將以一個簡單的實驗案例，一步一步的完成Vivado的整個設(shè)計流程一、新建工程1、打開Vivado 2013.4開發(fā)工具，可通過桌面快捷方式或開始菜單中xilinx DesignTools-Vivado 2013.4下的Vivado 2013.4打開軟件，開啟后，軟件如下所示：2、單擊上述界面中Create New Project圖標(biāo)，彈出新建工程向?qū)Вc擊Next.3、輸入工程名稱、選擇工程存儲路徑，并勾選Create project subdirectory選項，為工程在指定存儲路徑下建立獨立的文件夾。設(shè)置完成后，點擊Next注意：工程名稱和存儲路徑中不能出現(xiàn)中文和空格，建議工程名稱以字母、數(shù)字、下劃線來組成。4、選擇RTL Project一項，并勾選Do not specifty sources at this time，勾選該選項是為了跳過在新建工程的過程中添加設(shè)計源文件。點擊Next.IA5、根據(jù)使用的FPGA開發(fā)平臺，選擇對應(yīng)的FPGA目標(biāo)器件。（在本手冊中，以xilinx官方開發(fā)板KC705為例，Nexys4開發(fā)板請選擇Artix-7 XC7A100TCSG324-2的器件，即Family和Subfamily均為Artix-7，封裝形式（Package）為cSG324，速度等級（Speed grade）為-1，溫度等級（Temp Grade）為C）。點擊Next6、確認(rèn)相關(guān)信息與設(shè)計所用的的FPGA器件信息是否一致，一致請點擊Finish，不一致，請返回上一步修改。二、設(shè)計文件輸入1、如下圖所示，點擊Flow Navigator下的Project Manager->Add Sources或中間Sources中的對話框打開設(shè)計文件導(dǎo)入添加對話框。2、選擇第二項Add or Create Design Sources，用來添加或新建Verilog或VHDL源文件，點擊Next
標(biāo)簽： vivado
上傳時間： 2022-05-28
上傳用戶：默默
le flows through MOS channel while Ih flows across PNP transistor Ih= a/(1-a) le, IE-le+lh=1/(1-a)' le Since IGBT has a long base PNP, a is mainly determined by ar si0 2ar= 1/cosh(1/La), La: ambipolar diff length a-0.5 (typical value)p MOSFET channel current (saturation), le=U"Cox"W(2"Lch)"(Vc-Vth)le Thus, saturated collector current Ic, sat=1/(1-a)"le=-1/(1-a)"UCox"W/(2Lch)"(Vo-Vth)2Also, transconductance gm, gm= 1/(1-a)"u' Cox W/Lch*(Vo-Vth)Turn-On1. Inversion layer is formed when Vge>Vth2. Apply positive collector bias, +Vce3. Electrons flow from N+ emitter to N-drift layer providing the base current for the PNP transistor4. Since J1 is forward blased, hole carriers are injected from the collector (acts as an emitter).5. Injected hole carriers exceed the doping level of N-drift region (conductivity modulation). Turn-Off1. Remove gate bias (discharge gate)2. Cut off electron current (base current, le, of pnp transistor)
標(biāo)簽： igbt
上傳時間： 2022-06-20
上傳用戶：wangshoupeng199
This example shows how you can use signal functions in the Visiondebugger to simulate a signal that is coming into one of the analog inputs of the LPC21xx.The Measure example is described in detail in the Getting StartedUser's Guide.The MEASURE example program is available for several targets:Simulator: uVision Simulator for LPC2129MCB2100: Keil MCB2100 evaluation board with ULINK debugger - Application is loaded to internal Flash. - Switch S2 (INT1) is used as GPIO and sampled (jumper positions: J1= off, J7= on) - potentiometer POT1 is sampled as AIN0 (jumper position: J2= on) - serial port COM1 parameters: 9600 baud, no parity, 8-bits, 1 stop bit, flow control noneMCB2130: Keil MCB2130 evaluation board with ULINK debugger - Application is loaded to internal Flash. - Switch S2 (INT1) is used as GPIO and sampled (jumper positions: J1= off, J7= on) - potentiometer POT1 is sampled as AIN1 (jumper position: J2= on) - serial port COM1 parameters: 9600 baud, no parity, 8-bits, 1 stop bit, flow control none
標(biāo)簽： dac8568
上傳時間： 2022-06-28
上傳用戶：
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