This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
標(biāo)簽： 賽靈思 電機(jī)控制 開發(fā)套件 英文
上傳時(shí)間： 2013-10-28
上傳用戶：wujijunshi
An easy, yet highly-configurable iptables-based firewall solution designed for everybody from home users to network admins. Functionality for IPv6, tunneling, IPSec, and advanced routing is planned.
標(biāo)簽： highly-configurable iptables-based everybody designed
上傳時(shí)間： 2014-10-11
上傳用戶：huyiming139
介紹幾種cpuThe 8xC251SA/SB/SP/SQ improves on the MCS-51 architecture and peripheral features, introducing the advanced register based CPU architecture i.e., the MCS 251 microcontroller architecture. The register based CPU supports a 40-byte register file. In addition, the 8xC251SA/SB/SP/SQ microcontroller has 256-Kbyte expanded external code/data memory space and 64-Kbyte stack space. The new controller is also specially designed to execute C code efficiently. More importantly, the 8xC251SA/SB/SP/SQ maintains binary code compatibility with MCS 51 microcontrollers but at the same time allows the use of the powerful MCS 251 microcontroller instruction set, with many new 8, 16 and 32 bit instructions available. The 8xC251SA/SB/SP/SQ has 512 bytes or 1 Kbyte of on-chip data RAM options and is available in 16 Kbytes and 8 Kbytes of on-chip ROM/OTPROM or ROMless options.
標(biāo)簽： architecture introducin peripheral improves
上傳時(shí)間： 2015-03-15
上傳用戶：ccclll
Addressbook using double-linked list. This example shows the use of a double-linked list by implementing an addressbook for the console. It has features like inserting, searching(linear), sorting(bubble sort), deleting and load/save to a file. I wrote this during my study of Applied Computer Science so it s intended mainly for students who want to know about some advanced programming techniques in C. The Code was compiled with MSVC++ 6.0 but it should compile with any ANSI-compliant compiler.
標(biāo)簽： double-linked list Addressbook implemen
上傳時(shí)間： 2014-01-24
上傳用戶：asddsd
TMS Component Pack Pro Over 200 productivity VCL components, including grids, planning, scheduling, calendars, advanced edit controls, web update, enhanced listbox, treeview, combos, CAB file handling, and so much more
標(biāo)簽： productivity components scheduling Component
上傳時(shí)間： 2013-12-22
上傳用戶：caiiicc
... Samsung’s ARM 900 S3C2440 Specs. Tech NewsSamsung Semiconductor, Inc. Source: Convergence Promotions Mobile Applications ... Samsung’s S3C2440 is the industry’s fastest ARM9? family core-based application processor. With an advanced CPU Core
標(biāo)簽： Semiconductor NewsSamsung Convergence Samsung
上傳時(shí)間： 2014-01-25
上傳用戶：ljmwh2000
介紹高級(jí)數(shù)據(jù)結(jié)構(gòu)和算法的講義，advanced.zip
標(biāo)簽： 數(shù)據(jù)結(jié)構(gòu) 算法 講義
上傳時(shí)間： 2014-01-21
上傳用戶：athjac
一個(gè)由 php 寫成的開放源碼 會(huì)計(jì)/ERP/CRM 系統(tǒng)。它包含十九個(gè)模塊 - 系統(tǒng)管理，聯(lián)系資訊管理，顧客關(guān)系, 顧客自助服務(wù), 供應(yīng)商關(guān)系, 總帳，銀行結(jié)馀校對(duì)，存貨管理，服務(wù)管理，應(yīng)付帳/發(fā)票，應(yīng)收帳/發(fā)票，采購(gòu)訂單，銷售訂單，報(bào)價(jià)單，銷售點(diǎn)收銀員，銷售點(diǎn)主管，人力資源，職員自助服務(wù)和職員工資 包括一套新的顧客自助服務(wù)模塊，它提供了客戶服務(wù)中心和顧客研讀總帳報(bào)表等功能，安裝過(guò)程被改進(jìn)，對(duì)中文 egroupware 用戶來(lái)說(shuō)，zh/zt 被轉(zhuǎn)換到 utf-8 的功能被加入
上傳時(shí)間： 2015-05-22
上傳用戶：xinyuzhiqiwuwu
對(duì)工業(yè)生產(chǎn)過(guò)程結(jié)晶過(guò)程的一個(gè)仿真程序軟件包，具體描述可以參見文獻(xiàn)"Advanced control of crystallization processes"。
標(biāo)簽： 過(guò)程 工業(yè)生產(chǎn) 仿真程序 結(jié)晶
上傳時(shí)間： 2013-12-09
上傳用戶：zxc23456789
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