This Document provides the High Level Design specification for the Bootloader development and library porting for aDSP-BF533 based EZ-Kit Lite Board and STAMP Board. This document is meant to be the one of the inputs for the System Test Plan and the overall implementation of the same. This document also details the approach and assumptions made for the design
CF VHDL
The CF+ design was designed using the timing diagrams of the Compact Flash specification rev. 1.4, Analog Devices aDSP-218xN DSP Microcomputer specification, and the Intel StrataFlash Memory 28F320J3 specification.
