英文 網(wǎng)絡(luò)課件 Computer Networking: A Top Down Approach Featuring the Internet, 3rd edition. Jim Kurose, Keith Ross Addison-Wesley, July 2004.
標(biāo)簽： Networking Featuring Computer Approach
上傳時(shí)間： 2014-07-24
上傳用戶：123啊
A Top-Down Verilog-A Design on the digital phase-lockedmloop
標(biāo)簽： phase-lockedmloop Verilog-A Top-Down digital
上傳時(shí)間： 2013-12-02
上傳用戶：silenthink
用 2個(gè)鏈表 實(shí)現(xiàn) 鏈表 A 和鏈表 B相減并清楚重復(fù)內(nèi)容的程序
上傳時(shí)間： 2013-12-12
上傳用戶：Late_Li
包含了msp430單片機(jī)上的ADC、定時(shí)器A、定時(shí)器B、基礎(chǔ)時(shí)鐘、看門狗的初始化及中斷程序。基本示例程序
標(biāo)簽： msp 430 ADC 定時(shí)器
上傳時(shí)間： 2017-05-28
上傳用戶：qweqweqwe
computer networking a-top-down methods and Internet features 3th solution(english version)
標(biāo)簽： a-top-down networking computer Internet
上傳時(shí)間： 2014-09-03
上傳用戶：wangyi39
The algorithm ID3 (Quinlan) uses the method top-down induction of decision trees. Given a set of classified examples a decision tree is induced, biased by the information gain measure, which heuristically leads to small trees. The examples are given in attribute-value representation. The set of possible classes is finite. Only tests, that split the set of instances of the underlying example languages depending on the value of a single attribute are supported.
標(biāo)簽： algorithm induction decision top-down
上傳時(shí)間： 2017-08-20
上傳用戶：hzy5825468
This simple simulation of a pulse traveling down a parallel-plate guide makes a handy test code for initial experiments with boundary conditions. ToyFDTD3 adds some simple features to ToyFDTD1: A PMC boundary condition, a sinusoidal pulse source, and output tracking a single point in the mesh. Released 15 June 1999.
標(biāo)簽： parallel-plate simulation traveling simple
上傳時(shí)間： 2015-04-06
上傳用戶：stella2015
B樹及其B+樹的實(shí)現(xiàn)代碼，支持模版（數(shù)據(jù)類型，M值）
上傳時(shí)間： 2016-02-22
上傳用戶：jhksyghr
基于VHDL的SDH專用芯片的TOP-DOWN設(shè)計(jì)， 內(nèi)有全套源碼以及圖片，內(nèi)容詳盡，絕對(duì)真實(shí)可靠！
標(biāo)簽： TOP-DOWN VHDL SDH 專用芯片
上傳時(shí)間： 2013-12-11
上傳用戶：685
The DSKs or eZdspTM LF2407 and the DMC1500 make up a table top motor development system which allows engineers and software developers to evaluate certain characteristics of the TMS320F240, TMS320F243, and TMS320LF2407 DSPs to determine if the processor meets the designers application requirements. Evaluators can create software to execute onboard or expand the system in a variety of ways.
標(biāo)簽： development eZdspTM system allow
上傳時(shí)間： 2013-12-24
上傳用戶：zhuoying119
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