this is the documentation for intel processors, first Volume. it contains detailed specification and instrucion set - for hardcore programers on assembly
標簽： documentation specification processors contains
上傳時間： 2017-06-05
上傳用戶：希醬大魔王
the second Volume for intel processor documentation it continues first Volume with more processor acces code and specs
標簽： processor Volume documentation continues
上傳時間： 2017-06-05
上傳用戶：stewart·
PT2322 6 Channel Volume Control IC DATASHEET
標簽： DATASHEET Channel Control Volume
上傳時間： 2017-06-08
上傳用戶：evil
TMS320C54x DSP Reference Set Volume 2: Mnemonic Instruction Set
標簽： Instruction Reference Set Mnemonic
上傳時間： 2017-06-17
上傳用戶：zhangliming420
Symbian OS C++ for Mobile Phones Volume 2
標簽： Symbian Mobile Phones Volume
上傳時間： 2017-06-21
上傳用戶：koulian
This Volume presents the state of the art concerning quality and interestingness measures for data mining. The book summarizes recent developments and presents original research on this topic. The chapters include surveys, comparative studies of existing measures, proposals of new measures, simulations, and case studies. Both theoretical and applied chapters are included. Papers for this book were selected and reviewed for correctness and completeness by an international review committee.
標簽： interestingness concerning the presents
上傳時間： 2014-01-19
上傳用戶：ve3344
Thinking in C++ 2nd edition Volume 2: STL
標簽： Thinking edition Volume 2nd
上傳時間： 2013-12-22
上傳用戶：saharawalker
High Volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
標簽： technology 2.0 USB designed
上傳時間： 2014-01-02
上傳用戶：二驅蚊器
High Volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
標簽： technology 2.0 USB designed
上傳時間： 2017-07-05
上傳用戶：zhoujunzhen
Volume of fluid方法中的一種FCT方法的源代碼
上傳時間： 2017-07-07
上傳用戶：jing911003
