encode.v The encoder
syndrome.v Syndrome generator in decoder
berlekamp.v Berlekamp algorithm in decoder
chien-search.v Chien search and Forney algorithm in decoder
decode.v The top module of the decoder
inverse.v Computes multiplication inverse of an Galois field element
test-bench.v The test fixture, and some brief notes on using the modules.
data-rom.v A simple data source for testing
run For those intelligence-challenged who can t run verilog
LGPL The license
his project was built and tested with WinAVR-20060125.
Make sure the MCU target define in the Makefiles corresponds to the AVR you are using!!
To build the code, just install WinAVR and run "make" from the console in echomaster and
echoslave subdirs.
"make program" will program the device if you have a AVRISP attached.
Remember to set the AVR device to at least 8MHz. The AVR may use the programmable clock
from MC1319x, just remember to check if the MC1319x and SPI communication is working FIRST!
Otherwise you wont get any clock signal to the AVR and then you can t program it or reset
the fuses!
The MC1319x has default clock output of 32kHz so you will have to set your programmer to
a very low frequency (<=32kHz/4) to be able to program it while it is running on that!
關于FPGA流水線設計的論文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.
