USB接口控制器參考設計,xilinx提供VHDL代碼 usb xilinx vhdl ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 2 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
上傳時間： 2013-10-29
上傳用戶：zhouchang199
ref-sdr-sdram-vhdl代碼 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.
上傳時間： 2013-10-23
上傳用戶：半熟1994
UART 4 UART參考設計，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
上傳時間： 2013-11-02
上傳用戶：18862121743
各種功能的計數器實例（VHDL源代碼）:
上傳時間： 2013-10-19
上傳用戶：xanxuan
各種功能的計數器實例（VHDL源代碼）:ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; qa : OUT INTEGER RANGE 0 TO 255; qb : OUT INTEGER RANGE 0 TO 255; qc : OUT INTEGER RANGE 0 TO 255; qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255;
上傳時間： 2013-10-09
上傳用戶：松毓336
DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。
標簽： TESTBENCH VERILOG VHDL DES
上傳時間： 2015-01-04
上傳用戶：songyue1991
i2c總線的vhdl實現和vxworks的文件系統
上傳時間： 2015-01-06
上傳用戶：王小奇
8051核的vhdl原代碼。
上傳時間： 2015-01-08
上傳用戶：kikye
vhdl
標簽： vhdl
上傳時間： 2013-12-18
上傳用戶：pinksun9
vhdl
標簽： vhdl
上傳時間： 2015-01-08
上傳用戶：zaizaibang
