WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮點DSP算法實現方案: High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
上傳時間: 2013-10-21
上傳用戶:huql11633
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標簽: Efficient Verilog Digital Coding
上傳時間: 2013-11-23
上傳用戶:我干你啊
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上傳時間: 2013-11-20
上傳用戶:pzw421125
FPGAs have changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost sensitive designs. FPGAs had also been too expensive and tooslow for many applications, let alone for System Level Integration (SLI). Plus, the development
標簽: Methodology Design Reuse FPGA
上傳時間: 2013-11-01
上傳用戶:shawvi
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
標簽: CPLD
上傳時間: 2014-12-05
上傳用戶:qazxsw
We would like to welcome you as a user of the Allegro CX, a rugged, handheld fi eld PC for data collection. Developed with the input of data collection professionals worldwide, the Allegro CX is adaptable and versatile for use in a wide variety of data collection environments. The Allegro CX continues to utilize our ergonomic, lightweight design that is standard in our line of Allegro Field PCs. This design makes your Allegro easy to use for extended periods while moving to and from data collection sites in the fi eld.
上傳時間: 2015-01-02
上傳用戶:zhangyi99104144
數字與模擬電路設計技巧IC與LSI的功能大幅提升使得高壓電路與電力電路除外,幾乎所有的電路都是由半導體組件所構成,雖然半導體組件高速、高頻化時會有EMI的困擾,不過為了充分發揮半導體組件應有的性能,電路板設計與封裝技術仍具有決定性的影響。 模擬與數字技術的融合由于IC與LSI半導體本身的高速化,同時為了使機器達到正常動作的目的,因此技術上的跨越競爭越來越激烈。雖然構成系統的電路未必有clock設計,但是毫無疑問的是系統的可靠度是建立在電子組件的選用、封裝技術、電路設計與成本,以及如何防止噪訊的產生與噪訊外漏等綜合考慮。機器小型化、高速化、多功能化使得低頻/高頻、大功率信號/小功率信號、高輸出阻抗/低輸出阻抗、大電流/小電流、模擬/數字電路,經常出現在同一個高封裝密度電路板,設計者身處如此的環境必需面對前所未有的設計思維挑戰,例如高穩定性電路與吵雜(noisy)性電路為鄰時,如果未將噪訊入侵高穩定性電路的對策視為設計重點,事后反復的設計變更往往成為無解的夢魘。模擬電路與高速數字電路混合設計也是如此,假設微小模擬信號增幅后再將full scale 5V的模擬信號,利用10bit A/D轉換器轉換成數字信號,由于分割幅寬祇有4.9mV,因此要正確讀取該電壓level并非易事,結果造成10bit以上的A/D轉換器面臨無法順利運作的窘境。另一典型實例是使用示波器量測某數字電路基板兩點相隔10cm的ground電位,理論上ground電位應該是零,然而實際上卻可觀測到4.9mV數倍甚至數十倍的脈沖噪訊(pulse noise),如果該電位差是由模擬與數字混合電路的grand所造成的話,要測得4.9 mV的信號根本是不可能的事情,也就是說為了使模擬與數字混合電路順利動作,必需在封裝與電路設計有相對的對策,尤其是數字電路switching時,ground vance noise不會入侵analogue ground的防護對策,同時還需充分檢討各電路產生的電流回路(route)與電流大小,依此結果排除各種可能的干擾因素。以上介紹的實例都是設計模擬與數字混合電路時經常遇到的瓶頸,如果是設計12bit以上A/D轉換器時,它的困難度會更加復雜。
上傳時間: 2014-02-12
上傳用戶:wenyuoo
UART 4 UART參考設計,Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
上傳時間: 2013-11-02
上傳用戶:18862121743
The revolution of automation on factory floors is a key driver for the seemingly insatiable demand for higher productivity, lower total cost of ownership,and high safety. As a result, industrial applications drive an insatiable demand of higher data bandwidth and higher system-level performance. This white paper describes the trends and challenges seen by designers and how FPGAs enable solutions to meet their stringent design goals.
上傳時間: 2013-11-08
上傳用戶:yan2267246
Logger iButton devices have gained a lot of popularity with researchers. Although free evaluation software is easy to use and welldocumented, the choices and inputs that need to be made can sometimes be challenging. This application note explains technicalterms that are common with temperature logger iButtons and how they relate to each other. Additionally, it presents an algorithm tohelp users choose the necessary input parameters, including the sample rate based on a user's needs and the available memory tostore the data.
上傳時間: 2013-11-16
上傳用戶:xywhw1