第一步，拿到一塊PCB，首先在紙上記錄好所有元氣件的型號，參數，以及位置，尤其是二極管，三極管的方向，IC缺口的方向。最好用數碼相機拍兩張元氣件位置的照片。 第二步，拆掉所有器件，并且將PAD孔里的錫去掉。用酒精將PCB清洗干凈，然后放入掃描儀內，啟動POHTOSHOP，用彩色方式將絲印面掃入，并打印出來備用。 第三步，用水紗紙將TOP LAYER 和BOTTOM LAYER兩層輕微打磨，打磨到銅膜發亮，放入掃描儀，啟動PHOTOSHOP，用彩色方式將兩層分別掃入。注意，PCB在掃描儀內擺放一定要橫平樹直，否則掃描的圖象就無法使用，掃描儀分辨率請選為600。 需要的朋友請下載哦！
上傳時間： 2014-03-04
上傳用戶：tianming222
This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horizontal resolution, and implementation options. The rank to be selected can bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a fully synchronous interface through the ce, clk,and rst ports.
上傳時間： 2013-12-14
上傳用戶：逗逗666
MP3 portable players are the trend in music-listening technology. These players do not includeany mechanical movements, thereby making them ideal for listening to music during any type ofactivity. MP3 is a digital compression technique based on MPEG Layer 3 which stores music ina lot less space than current CD technology. Software is readily available to create MP3 filesfrom an existing CD, and the user can then download these files into a portable MP3 player tobe enjoyed in almost any environment.
上傳時間： 2013-11-23
上傳用戶：nanxia
Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
上傳時間： 2013-10-22
上傳用戶：aeiouetla
波長信號的解調是實現光纖光柵傳感網絡的關鍵，基于現有的光纖光柵傳感器解調方法，提出一種基于FPGA的雙匹配光纖光柵解調方法，此系統是一種高速率、高精度、低成本的解調系統，并且通過引入雙匹配光柵有效地克服了雙值問題同時擴大了檢測范圍。分析了光纖光柵的測溫原理并給出了該方案軟硬件設計，綜合考慮系統的解調精度和FPGA的處理速度給出了基于拉格朗日的曲線擬合算法。 Abstract: Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This paper analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this paper gives the curve fitting algorithm based on Lagrange.
上傳時間： 2013-10-10
上傳用戶：zxc23456789
第一步，拿到一塊PCB，首先在紙上記錄好所有元氣件的型號，參數，以及位置，尤其是二極管，三機管的方向，IC缺口的方向。最好用數碼相機拍兩張元氣件位置的照片。第二步，拆掉所有器件，并且將PAD孔里的錫去掉。用酒精將PCB清洗干凈，然后放入掃描儀內，啟動POHTOSHOP，用彩色方式將絲印面掃入，并打印出來備用。第三步，用水紗紙將TOP LAYER 和BOTTOM LAYER兩層輕微打磨，打磨到銅膜發亮，放入掃描儀，啟動PHOTOSHOP，用彩色方式將兩層分別掃入。注意，PCB在掃描儀內擺放一定要橫平樹直，否則掃描的圖象就無法使用。第四步，調整畫布的對比度，明暗度，使有銅膜的部分和沒有銅膜的部分對比強烈，然后將次圖轉為黑白色，檢查線條是否清晰，如果不清晰，則重復本步驟。如果清晰，將圖存為黑白BMP格式文件TOP.BMP和BOT.BMP。第五步，將兩個BMP格式的文件分別轉為PROTEL格式文件，在PROTEL中調入兩層，如過兩層的PAD和VIA的位置基本重合，表明前幾個步驟做的很好，如果有偏差，則重復第三步。第六，將TOP。BMP轉化為TOP。PCB，注意要轉化到SILK層，就是黃色的那層，然后你在TOP層描線就是了，并且根據第二步的圖紙放置器件。畫完后將SILK層刪掉。 第七步，將BOT。BMP轉化為BOT。PCB，注意要轉化到SILK層，就是黃色的那層，然后你在BOT層描線就是了。畫完后將SILK層刪掉。第八步，在PROTEL中將TOP。PCB和BOT。PCB調入，合為一個圖就OK了。第九步，用激光打印機將TOP LAYER， BOTTOM LAYER分別打印到透明膠片上（1：1的比例），把膠片放到那塊PCB上，比較一下是否有誤，如果沒錯，你就大功告成了。
上傳時間： 2013-11-24
上傳用戶：ynzfm
PCB LAYOUT 術語解釋(TERMS)1. COMPONENT SIDE(零件面、正面)︰大多數零件放置之面。2. SOLDER SIDE(焊錫面、反面)。3. SOLDER MASK(止焊膜面)︰通常指Solder Mask Open 之意。4. TOP PAD︰在零件面上所設計之零件腳PAD，不管是否鑽孔、電鍍。5. BOTTOM PAD：在銲錫面上所設計之零件腳PAD，不管是否鑽孔、電鍍。6. POSITIVE LAYER：單、雙層板之各層線路；多層板之上、下兩層線路及內層走線皆屬之。7. NEGATIVE LAYER：通常指多層板之電源層。8. INNER PAD：多層板之POSITIVE LAYER 內層PAD。9. ANTI-PAD：多層板之NEGATIVE LAYER 上所使用之絕緣範圍，不與零件腳相接。10. THERMAL PAD：多層板內NEGATIVE LAYER 上必須零件腳時所使用之PAD，一般稱為散熱孔或導通孔。11. PAD (銲墊)：除了SMD PAD 外，其他PAD 之TOP PAD、BOTTOM PAD 及INNER PAD 之形狀大小皆應相同。12. Moat : 不同信號的 Power& GND plane 之間的分隔線13. Grid : 佈線時的走線格點2. Test Point : ATE 測試點供工廠ICT 測試治具使用ICT 測試點 LAYOUT 注意事項:PCB 的每條TRACE 都要有一個作為測試用之TEST PAD(測試點)，其原則如下：1. 一般測試點大小均為30-35mil，元件分布較密時，測試點最小可至30mil.測試點與元件PAD 的距離最小為40mil。2. 測試點與測試點間的間距最小為50-75mil，一般使用75mil。密度高時可使用50mil,3. 測試點必須均勻分佈於PCB 上，避免測試時造成板面受力不均。4. 多層板必須透過貫穿孔(VIA)將測試點留於錫爐著錫面上(Solder Side)。5. 測試點必需放至於Bottom Layer6. 輸出test point report(.asc 檔案powerpcb v3.5)供廠商分析可測率7. 測試點設置處:Setuppadsstacks
上傳時間： 2013-11-17
上傳用戶：cjf0304
LAYOUT REPORT .............. 1 目錄.................. 1 1. PCB LAYOUT 術語解釋(TERMS)......... 2 2. Test Point : ATE 測試點供工廠ICT 測試治具使用............ 2 3. 基準點 (光學點) -for SMD:........... 4 4. 標記 (LABEL ING)......... 5 5. VIA HOLE PAD................. 5 6. PCB Layer 排列方式...... 5 7.零件佈置注意事項 (PLACEMENT NOTES)............... 5 8. PCB LAYOUT 設計............ 6 9. Transmission Line ( 傳輸線 )..... 8 10.General Guidelines – 跨Plane.. 8 11. General Guidelines – 繞線....... 9 12. General Guidelines – Damping Resistor. 10 13. General Guidelines - RJ45 to Transformer................. 10 14. Clock Routing Guideline........... 12 15. OSC & CRYSTAL Guideline........... 12 16. CPU
上傳時間： 2013-10-29
上傳用戶：1234xhb
Abstract: As industrial control systems (ICSs) have become increasingly connected and use more off-the-shelfcomponents, new vulnerabilities to cyber attacks have emerged. This tutorial looks at three types of ICSs:programmable logic controllers (PLCs), supervisory control and data acquisition (SCADA) systems, anddistributed control systems (DCSs), and then discusses security issues and remedies. This document alsoexplains the benefits and limitations of two cryptographic solutions (digital signatures and encryption) andelaborates on the reasons for using security ICs in an ICS to support cryptography.
上傳時間： 2013-10-09
上傳用戶：woshinimiaoye
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上傳時間： 2013-12-25
上傳用戶：jkhjkh1982
