Linux中Input輸入子系統(tǒng)分析(pdf)
標(biāo)簽： linux
上傳時(shí)間： 2015-04-10
上傳用戶(hù)：zsp26414609
The writing of this book was prompted by two main developments in wireless communications in the past decade. First is the huge surge of research activities in physical-layer wireless communication theory. While this has been a subject of study since the 60’s, recent developments in the field, such as opportunistic and multi-input multi-output (MIMO) communication techniques, have brought completely new per- spectives on how to communicate over wireless channels.
標(biāo)簽： Communication Fundamentals Wireless of
上傳時(shí)間： 2020-05-27
上傳用戶(hù)：shancjb
Many wireless communications channels consist of multiple signal paths from the transmitter to receiver. This multiplicity of paths leads to a phenomenon known as multipath fading. The multiple paths are caused by the presence of objects in the physical environment that, through the mechanisms of propagation, alter the path of radiated energy. These objects are referred to as scatterers. In the past, researchers often looked at ways to mitigate multipath scattering, such as in diversity systems. Multiple-input, multiple-output (MIMO) systems, on the other hand, use multipath diversity to their advantage; a MIMO system has the ability to translate increased spatial diversity into increased channel capacity.
標(biāo)簽： Multiple-Output Multiple-Input Channel Models
上傳時(shí)間： 2020-05-31
上傳用戶(hù)：shancjb
The purpose of this book is to present detailed fundamental information on a global positioning system (GPS) receiver. Although GPS receivers are popu- larly used in every-day life, their operation principles cannot be easily found in one book. Most other types of receivers process the input signals to obtain the necessary information easily, such as in amplitude modulation (AM) and frequency modulation (FM) radios. In a GPS receiver the signal is processed to obtain the required information, which in turn is used to calculate the user position. Therefore, at least two areas of discipline, receiver technology and navigation scheme, are employed in a GPS receiver. This book covers both areas.
標(biāo)簽： Fundamentals_of_Global_Positionin g_System_Receivers
上傳時(shí)間： 2020-06-09
上傳用戶(hù)：shancjb
The PW5410B is a low noise, constant frequency (1.2MHz) switched capacitor voltage doubler. Itproduces a regulated output voltage from 1.8V to 5V input with up to 100mA of output current. Lowexternal parts count (one flying capacitor and two small bypass capacitors at VIN and VOUT) makethe PW5410B ideally suited for small, battery-powered applications
標(biāo)簽： pw5410
上傳時(shí)間： 2022-02-11
上傳用戶(hù)：wangshoupeng199
The PW5410A is a low noise, constant frequency (1.2MHz) switched capacitor voltage doubler. Itproduces a regulated output voltage from 2.7V to 5V input with up to 250mA of output current. Lowexternal parts count (one flying capacitor and two small bypass capacitors at VIN and VOUT) makethe PW5410A ideally suited for small, battery-powered applications
標(biāo)簽： pw5410
上傳時(shí)間： 2022-02-11
上傳用戶(hù)：
LED 線(xiàn)陣顯示裝置, 分為 LED 線(xiàn)性旋轉(zhuǎn)顯示主機(jī)和圖文錄入器兩部分。主機(jī)用直流電機(jī)帶動(dòng)由紅綠 LED 組成的線(xiàn)陣旋轉(zhuǎn), 同時(shí)線(xiàn)陣按照時(shí)序依次切換顯示狀態(tài), 在固定區(qū)域利用視覺(jué)暫留效果形成 16×16 點(diǎn)陣, 用以顯示圖文;圖文錄入器用 HMI 觸控屏作為人機(jī)交互界面, 實(shí)現(xiàn)圖文錄入和回放功能。主機(jī)與圖文錄入器通過(guò)無(wú)線(xiàn)通信方式進(jìn)行信息交互,可由圖文錄入器控制主機(jī)切換不同工作任務(wù), 以及改變線(xiàn)陣顯示內(nèi)容。The LED linear array display device is divided into two parts:the one is the main unit used to display content,and the other one is used to input the contents.The main unit is driven by a DC motor to rotate the linear array composed by red and green light emitting diodes.At the same time,the 16×16 dot matrix that switching the display state according to the time sequence on the main unit displays pictures and texts in the fixed area,by using the visual temporary effect.The HMI touch screen is used as human machine interface to realize the function that input and playback pictures and texts.The two parts of the device communicate with each other through wireless communication.The image and text input controller can control the main unit to switch different tasks and change the content of linear array displayed.
標(biāo)簽： stc12c5a60s2 單片機(jī) led
上傳時(shí)間： 2022-03-28
上傳用戶(hù)：jiabin
近些年來(lái)，隨著電力電子技術(shù)的發(fā)展，電力電子系統(tǒng)集成受到越來(lái)越多的關(guān)注，其中標(biāo)準(zhǔn)化模塊的串并聯(lián)技術(shù)成為研究熱點(diǎn)之一。輸入并聯(lián)輸出串聯(lián)型(Input-Parallel and Output-Series，IPOS)組合變換器適用于大功率高輸出電壓的場(chǎng)合。 要保證IPOS組合變換器正常工作，必須保證其各模塊的輸出電壓均衡。本文首先揭示了IPOS組合變換器中每個(gè)模塊輸入電流均分和輸出電壓均分之間的關(guān)系，在此基礎(chǔ)上提出一種輸出均壓控制方案，該方案對(duì)系統(tǒng)輸出電壓調(diào)節(jié)沒(méi)有影響。選擇移相控制全橋(Full-Bridge，F(xiàn)B)變換器作為基本模塊，對(duì)n個(gè)全橋模塊組成的IPOS組合變換器建立小信號(hào)數(shù)學(xué)模型，推導(dǎo)出采用輸出均壓控制方案的IPOS-FB系統(tǒng)的數(shù)學(xué)模型，該模型證明各模塊輸出均壓閉環(huán)不影響系統(tǒng)輸出電壓閉環(huán)的調(diào)節(jié)，給出了模塊輸出均壓閉環(huán)和系統(tǒng)輸出電壓閉環(huán)的補(bǔ)償網(wǎng)絡(luò)參數(shù)設(shè)計(jì)。對(duì)于IPOS組合變換器，采用交錯(cuò)控制，由于電流紋波抵消效應(yīng)，輸入濾波電容容量可大大減小；由于電壓紋波抵消作用，在相同的系統(tǒng)輸出電壓紋波下，各模塊的輸出濾波電容可大大減小，由此可以提高變換器的功率密度。 根據(jù)所提出的輸出均壓控制策略，在實(shí)驗(yàn)室研制了一臺(tái)由兩個(gè)1kW全橋模塊組成的IPOS-FB原理樣機(jī)，每個(gè)模塊輸入電壓為270V，輸出電壓為180V。并進(jìn)行了仿真和實(shí)驗(yàn)驗(yàn)證，結(jié)果均表明本控制方案是正確有效的。
標(biāo)簽： 輸入 并聯(lián) 串聯(lián)
上傳時(shí)間： 2013-06-17
上傳用戶(hù)：cwyd0822
現(xiàn)場(chǎng)可編程門(mén)陣列(FPGA，F(xiàn)ield Programmable Gate Array)是可編程邏輯器件的一種，它的出現(xiàn)是隨著微電子技術(shù)的發(fā)展，設(shè)計(jì)與制造集成電路的任務(wù)已不完全由半導(dǎo)體廠商來(lái)獨(dú)立承擔(dān)。系統(tǒng)設(shè)計(jì)師們更愿意自己設(shè)計(jì)專(zhuān)用集成電路(ASIC，Application Specific Integrated Circuit)．芯片，而且希望ASIC的設(shè)計(jì)周期盡可能短，最好是在實(shí)驗(yàn)室里就能設(shè)計(jì)出合適的ASIC芯片，并且立即投入實(shí)際應(yīng)用之中。現(xiàn)在，F(xiàn)PGA已廣泛地運(yùn)用于通信領(lǐng)域、消費(fèi)類(lèi)電子和車(chē)用電子。 本文中涉及的I/O端口模塊是FPGA中最主要的幾個(gè)大模塊之一，它的主要作用是提供封裝引腳到CLB之間的接口，將外部信號(hào)引入FPGA內(nèi)部進(jìn)行邏輯功能的實(shí)現(xiàn)并把結(jié)果輸出給外部電路，并且根據(jù)需要可以進(jìn)行配置來(lái)支持多種不同的接口標(biāo)準(zhǔn)。FPGA允許使用者通過(guò)不同編程來(lái)配置實(shí)現(xiàn)各種邏輯功能，在IO端口中它可以通過(guò)選擇配置方式來(lái)兼容不同信號(hào)標(biāo)準(zhǔn)的I/O緩沖器電路。總體而言，可選的I/O資源的特性包括：IO標(biāo)準(zhǔn)的選擇、輸出驅(qū)動(dòng)能力的編程控制、擺率選擇、輸入延遲和維持時(shí)間控制等。 本文是關(guān)于FPGA中多標(biāo)準(zhǔn)兼容可編程輸入輸出電路(Input/Output Block)的設(shè)計(jì)和實(shí)現(xiàn)，該課題是成都華微電子系統(tǒng)有限公司FPGA大項(xiàng)目中的一子項(xiàng)，目的為在更新的工藝水平上設(shè)計(jì)出能夠兼容單端標(biāo)準(zhǔn)的I/O電路模塊；同時(shí)針對(duì)以前設(shè)計(jì)的I/O模塊不支持雙端標(biāo)準(zhǔn)的缺點(diǎn)，要求新的電路模塊中擴(kuò)展出雙端標(biāo)準(zhǔn)的部分。文中以低壓雙端差分標(biāo)準(zhǔn)(LVDS)為代表構(gòu)建雙端標(biāo)準(zhǔn)收發(fā)轉(zhuǎn)換電路，與單端標(biāo)準(zhǔn)比較，LVDS具有很多優(yōu)點(diǎn)： (1)LVDS傳輸?shù)男盘?hào)擺幅小，從而功耗低，一般差分線(xiàn)上電流不超過(guò)4mA，負(fù)載阻抗為100Ω。這一特征使它適合做并行數(shù)據(jù)傳輸。 (2)LVDS信號(hào)擺幅小，從而使得該結(jié)構(gòu)可以在2.5V的低電壓下工作。 (3)LVDS輸入單端信號(hào)電壓可以從0V到2.4V變化，單端信號(hào)擺幅為400mV，這樣允許輸入共模電壓從0.2V到2.2V范圍內(nèi)變化，也就是說(shuō)LVDS允許收發(fā)兩端地電勢(shì)有±1V的落差。 本文采用0.18μm1.8V/3.3V混合工藝，輔助Xilinx公司FPGA開(kāi)發(fā)軟件ISE，設(shè)計(jì)完成了可以用于Virtex系列各低端型號(hào)FPGA的IOB結(jié)構(gòu)，它有靈活的可配置性和出色的適應(yīng)能力，能支持大量的I/O標(biāo)準(zhǔn)，其中包括單端標(biāo)準(zhǔn)，也包括雙端標(biāo)準(zhǔn)如LVDS等。它具有適應(yīng)性的優(yōu)點(diǎn)、可選的特性和考慮到被文件描述的硬件結(jié)構(gòu)特征，這些特點(diǎn)可以改進(jìn)和簡(jiǎn)化系統(tǒng)級(jí)的設(shè)計(jì)，為最終的產(chǎn)品設(shè)計(jì)和生產(chǎn)打下基礎(chǔ)。設(shè)計(jì)中對(duì)包括20種IO標(biāo)準(zhǔn)在內(nèi)的各電器參數(shù)按照用戶(hù)手冊(cè)描述進(jìn)行仿真驗(yàn)證，性能參數(shù)已達(dá)到預(yù)期標(biāo)準(zhǔn)。
標(biāo)簽： FPGA 標(biāo)準(zhǔn) 可編程
上傳時(shí)間： 2013-05-15
上傳用戶(hù)：shawvi
To get started with Code Composer Studio? (CCStudio) Development Tools, review the first two sections of this book. The remaining sections contain more detailed information on specific processes and tools. To determine whether you can utilize these features, see the online help provided with the Code Composer Studio installation.
上傳時(shí)間： 2013-07-24
上傳用戶(hù)：zaizaibang
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
