This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-14
上傳用戶：fdmpy
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
8051 Serial I/O Routines Ring buffered, interrupt-driven UART driver, written in Keil C .
標(biāo)簽： interrupt-driven Routines buffered written
上傳時(shí)間： 2013-11-27
上傳用戶：330402686
test program for STL generic algorithm that search for elements that satisfy a condition
標(biāo)簽： that for algorithm condition
上傳時(shí)間： 2013-12-14
上傳用戶：咔樂塢
test SNMP JAVA
上傳時(shí)間： 2015-01-21
上傳用戶：qilin
java test program
上傳時(shí)間： 2015-01-23
上傳用戶：Andy123456
JSP 文件管理器,演示測試帳號(hào):test 密碼:test
上傳時(shí)間： 2015-01-23
上傳用戶：cuiyashuo
Filename: main.c * Description: A simple test program for the CRC implementations. * Notes: To test a different CRC standard, modify crc.h. * * * Copyright (c) 2000 by Michael Barr. This software is placed into * the public domain and may be used for any purpose. However, this * notice must not be changed or removed and no warranty is either * expressed or implied by its publication or distribution.
標(biāo)簽： test implementations Description Filename
上傳時(shí)間： 2015-02-02
上傳用戶：leehom61
mcu for video conference test
標(biāo)簽： conference video test mcu
上傳時(shí)間： 2015-02-04
上傳用戶：Miyuki
softphone client for test
標(biāo)簽： softphone client test for
上傳時(shí)間： 2015-02-04
上傳用戶：wff
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