Spartan-3E Starter Kit Board User Guide英語版的介紹，很適合初學(xué)者學(xué)習(xí)學(xué)習(xí)
標(biāo)簽： Spartan Starter Board Guide
上傳時(shí)間： 2013-11-19
上傳用戶：ruan2570406
This application note provides a detailed description of the Spartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the part. Additionally, a methodology ispresented that will guide the user through the readback process. This information can be usedfor partial reconfiguration or partial readback.
標(biāo)簽： Spartan XAPP 452 架構(gòu)
上傳時(shí)間： 2013-11-16
上傳用戶：qingdou
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
標(biāo)簽： Spartan-XL Express XAPP FPGA
上傳時(shí)間： 2015-01-02
上傳用戶：nanxia
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
標(biāo)簽： Spartan XAPP FPGA 098
上傳時(shí)間： 2013-11-01
上傳用戶：wojiaohs
FPGA 具有輕松集成與支持新協(xié)議和新標(biāo)準(zhǔn)以及產(chǎn)品定制的能力，同時(shí)仍然可以實(shí)現(xiàn)快速的產(chǎn)品面市時(shí)間。在互聯(lián)網(wǎng)和全球市場環(huán)境中，外包制造變得越來越普遍，這使得安全變得更加重要。正如業(yè)界領(lǐng)袖出版的文章所述，反向工程、克隆、過度構(gòu)建以及篡改已經(jīng)成為主要的安全問題。據(jù)專家估計(jì)，每年因?yàn)榧倜爱a(chǎn)品而造成的經(jīng)濟(jì)損失達(dá)數(shù)十億美元。國際反盜版聯(lián)盟表示，這些假冒產(chǎn)品威脅經(jīng)濟(jì)的發(fā)展，并且給全球的消費(fèi)類市場帶來重大影響。本白皮書將確定設(shè)計(jì)安全所面臨的主要威脅，探討高級(jí)安全選擇，并且介紹Xilinx 的新型、低成本SpartanTM-3A、Spartan-3AN 和Spartan-3A DSP FPGA 如何協(xié)助保護(hù)您的產(chǎn)品和利潤。
標(biāo)簽： Spartan FPGA 267 DSP
上傳時(shí)間： 2013-10-26
上傳用戶：simonpeng
Spartan-3AN 器件帶有可以用于儲(chǔ)存配置數(shù)據(jù)的片上Flash 存儲(chǔ)器。如果在您的設(shè)計(jì)中Flash 存儲(chǔ)器沒有與外部相連，那么Flash 存儲(chǔ)器無法從I/O 引腳讀取數(shù)據(jù)。由于Flash 存儲(chǔ)器在FPGA 內(nèi)部，因此配置過程中Spartan-3AN 器件比特流處于隱藏狀態(tài)。這一配置成了設(shè)計(jì)安全的起點(diǎn)，因?yàn)闊o法直接從Flash 存儲(chǔ)器拷貝設(shè)計(jì)。
上傳時(shí)間： 2013-10-31
上傳用戶：R50974
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
標(biāo)簽： CoolRunner-II XAPP CPLD 380
上傳時(shí)間： 2013-10-26
上傳用戶：kiklkook
The introduction of Spartan-3™ devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gates, and under $5for 100K gate-level units, any design with programmablelogic has a readily available 8- or 16-bit processor costingless than 75 cents and 32-bit processor for less than $1.50.
上傳時(shí)間： 2013-10-21
上傳用戶：ligi201200
This application note shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining CPLD resources
標(biāo)簽： CoolRunner-II Xilinx XAPP CPLD
上傳時(shí)間： 2013-12-16
上傳用戶：qwer0574
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application note uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
標(biāo)簽： Spartan XAPP 1065 FPGA
上傳時(shí)間： 2013-11-01
上傳用戶：hjkhjk
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