The software and hardware development fields evolved along Separate paths through the end of the 20th century. We seem to have come full circle, however. The previously rigid hardware on which our programs run is softening in many ways. Embedded systems are largely responsible for this softening. These hidden computing systems drive the electronic products around us, including consumer products like digital cameras and personal digital assistants, office automation equipment like copy machines and printers, medical devices like heart monitors and ventilators, and automotive electronics like cruise controls and antilock brakes. Embedded systems force designers to work under incredibly tight time-tomarket, power consumption, size, performance, flexibility, and cost constraints. Many technologies introduced over the past two decades have sought to help satisfy these constraints. To understand these technologies, it is important to first distinguish the underlying embedded systems elements.
標簽： development the software hardware
上傳時間： 2017-08-15
上傳用戶：cjf0304
The Reactor design pattern handles service requests that are delivered concurrently to an application by one or more clients. Each service in an application may consist of serveral methods and is represented by a Separate event handler that is responsible for dispatching service-specific requests.
上傳時間： 2013-10-15
上傳用戶：libinxny
In an increasing trend, telecommunications, networking,audio and instrumentation require low noise power supplies.In particular, there is interest in low noise, lowdropout linear regulators (LDO). These components powernoise-sensitive circuitry, circuitry that contains noisesensitiveelements or both. Additionally, to conserve power,particularly in battery driven apparatus such as cellulartelephones, the regulators must operate with low input-tooutputvoltages.1 Devices presently becoming availablemeet these requirements (see Separate section, “A Familyof 20mVRMS Noise, Low Dropout Regulators”).
標簽： 低噪聲 低壓差穩(wěn)壓器 性能
上傳時間： 2013-10-30
上傳用戶：yeling1919
針對科研實驗中對拉壓千斤頂加載過程控制的需要，采用ATmega128單片機控制步進電機進而實現(xiàn)對執(zhí)行系統(tǒng)的電動泵站實行自動控制。對力和位移的數(shù)據(jù)采集與處理及用步進電機控制電動泵站手柄的技術細節(jié)作了重點描述。通過單片機的A/D變換器對AMP放大模塊采集的電橋信號作量化處理，千斤頂?shù)牟倏厥直恢靡离妱佑捅瞄y門開啟的方向和大小作若干定位，單片機根據(jù)力或位移傳感器信號，實時控制步進電機驅(qū)動手柄旋轉(zhuǎn)到相應操控位置。 Abstract: This article describes the use of ATmega128 AVR microcontroller series of DBS electric pumping stations and QF100/200 Separate twoway hydraulic jack to automate the process of manipulating the work of the technical content. Articles on force and displacement data acquisition and processing， and stepper motor control electric pump with the handle of the key technical details were described. Through the MCU’s A / D converter module is collected on the AMP amplification quantify the signal bridge， jack handle position control valve opening according to the direction of electric pumps for a number of positioning and size of the microcontroller based on force or displacement sensor signals， real-time control stepper motor drive control handle rotate to the appropriate location.
標簽： AVR 單片機 閉環(huán)控制
上傳時間： 2014-01-16
上傳用戶：hasan2015
The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on Separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.
上傳時間： 2013-10-09
上傳用戶：3294322651
The P82B96 offers many different ways in which it can be used as abus interface. In its simplest application it can be used as aninterface between bus systems operating from different supplyvoltages. Opto isolation between two bus systems is possible, andalso the availability of the Tx and Rx signals permits interfacing ofthe P82B96 with other bus systems which Separate the forwardoutput path, from the backward input signal path.
上傳時間： 2013-10-11
上傳用戶：洛木卓
The 87C576 includes two Separate methods of programming theEPROM array, the traditional modified Quick-Pulse method, and anew On-Board Programming technique (OBP).Quick Pulse programming is a method using a number of devicepins in parallel (see Figure 1) and is the traditional way in which87C51 family members have been programmed. The Quick-Pulsemethod supports the following programming functions:– program USER EPROM– verify USER EPROM– program KEY EPROM– program security bits– verify security bits– read signature bytesThe Quick-Pulse method is quite easily suited to standardprogramming equipment as evidenced by the numerous vendors of87C51 compatible programmers on the market today. Onedisadvantage is that this method is not well suited to programming inthe embedded application because of the large number of signallines that must be isolated from the application. In addition, parallelsignals from a programmer would need to be cabled to theapplication’s circuit board, or the application circuit board wouldneed to have logic built-in to perform the programming functions.These requirements have generally made in-circuit programmingusing the modified Quick Pulse method impractical in almost all87C51 family applications.
上傳時間： 2013-10-21
上傳用戶：xiaozhiqban
針對UHF讀寫器設計中，在符合EPC Gen2標準的情況下，對標簽返回的高速數(shù)據(jù)進行正確解碼以達到正確讀取標簽的要求，提出了一種新的在ARM平臺下采用邊沿捕獲統(tǒng)計定時器數(shù)判斷數(shù)據(jù)的方法，并對FM0編碼進行解碼。與傳統(tǒng)的使用定時器定時采樣高低電平的FM0解碼方法相比，該解碼方法可以減少定時器定時誤差累積的影響；可以將捕獲定時器數(shù)中斷與數(shù)據(jù)判斷解碼相對分隔開，使得中斷對解碼影響很小，實現(xiàn)捕獲與解碼的同步。通過實驗表明，這種方法提高了解碼的效率，在160 Kb/s的接收速度下，讀取一張標簽的時間約為30次/s。 Abstract: Aiming at the requirement of receiving correctly decoded data from the tag under high-speed communication which complied with EPC Gen2 standard in the design of UHF interrogator， the article introduced a new technology for FM0 decoding which counted the timer counter to judge data by using the edge interval of signal capture based on the ARM7 platform. Compared with the traditional FM0 decoding method which used the timer timed to sample the high and low level， the method could reduce the accumulation of timing error and could relatively Separate capture timer interrupt and the data judgment for decoding， so that the disruption effect on the decoding was small and realizd synchronization of capture and decoding. Testing result shows that the method improves the efficiency of decoding， at 160 Kb/s receiving speed， the time of the interrogator to read a tag is about 30 times/s.
上傳時間： 2013-11-10
上傳用戶：liufei
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withSeparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
標簽： Cortex-M 1850 LPC 內(nèi)核微控制器
上傳時間： 2014-12-31
上傳用戶：zhuoying119
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withSeparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時間： 2013-10-28
上傳用戶：15501536189
