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Sensitive

  • 100-15V TO 12V DCDC 原理圖 PCB BOM表

    高的工作電壓高達(dá)100V N雙N溝道MOSFET同步驅(qū)動 The D810DCDC is a synchronous step-down switching regulator controller that can directly step-down voltages from up to 100V, making it ideal for telecom and automotive applications. The D810DCDC uses a constant on-time valley current control architecture to deliver very low duty cycles with accurate cycle-by-cycle current limit, without requiring a sense resistor. A precise internal reference provides 0.5% DC accuracy. A high bandwidth (25MHz) error amplifi er provides very fast line and load transient response. Large 1Ω gate drivers allow the D810DCDC to drive multiple MOSFETs for higher current applications. The operating frequency is selected by an external resistor and is compensated for variations in VIN and can also be synchronized to an external clock for switching-noise Sensitive applications. Integrated bias control generates gate drive power from the input supply during start-up and when an output shortcircuit occurs, with the addition of a small external SOT23 MOSFET. When in regulation, power is derived from the output for higher effi ciency.

    標(biāo)簽: DCDC 100 12V BOM

    上傳時(shí)間: 2013-10-24

    上傳用戶:wd450412225

  • 低噪聲,低壓差穩(wěn)壓器的性能驗(yàn)證

      In an increasing trend, telecommunications, networking,audio and instrumentation require low noise power supplies.In particular, there is interest in low noise, lowdropout linear regulators (LDO). These components powernoise-Sensitive circuitry, circuitry that contains noiseSensitiveelements or both. Additionally, to conserve power,particularly in battery driven apparatus such as cellulartelephones, the regulators must operate with low input-tooutputvoltages.1 Devices presently becoming availablemeet these requirements (see separate section, “A Familyof 20mVRMS Noise, Low Dropout Regulators”).

    標(biāo)簽: 低噪聲 低壓差穩(wěn)壓器 性能

    上傳時(shí)間: 2013-10-30

    上傳用戶:yeling1919

  • MC9S08QG8英文資料 pdf

    MC9S08QG8英文資料 The MC9S08QG8 is the newest member of the Freescale 8-bit family of highly integratedmicrocontrollers, based on the high-performance yet low power HCS08 core. The MC9S08QG8is an excellent solution for power-Sensitive applications with extended battery life and maximum performance down to 1.8VDC.

    標(biāo)簽: MC9 S08 QG8

    上傳時(shí)間: 2014-12-28

    上傳用戶:dxxx

  • Clocking Options for Stellaris

    The main oscillator allows either a crystal or single-ended input clock signal. Cost-Sensitiveapplications typically use an external crystal with the on-chip oscillator circuit since it is the mostcost-effective solution. It is also possible to use the internal oscillator to clock the device after theboot process has completed.

    標(biāo)簽: Stellaris Clocking Options for

    上傳時(shí)間: 2013-10-14

    上傳用戶:pol123

  • DUAL DIGITAL ISOLATORS

    The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are orientedin the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic inputand output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to4000 V. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, andprevent noise currents on a data bus or other circuits from entering the local ground and interfering with ordamaging Sensitive circuitry.

    標(biāo)簽: ISOLATORS DIGITAL DUAL

    上傳時(shí)間: 2013-10-24

    上傳用戶:hbsunhui

  • 水位監(jiān)測報(bào)警系統(tǒng)原理

    摘要:本水位監(jiān)測報(bào)警器使用5V低壓直流電源(也可以用3節(jié)5號電池代替)就可以對5~15厘米的水位進(jìn)行監(jiān)測,用LED顯示和數(shù)碼管顯示水位,并可以對不再此范圍內(nèi)的水位發(fā)出報(bào)警。主要采用CD4066、74LS86、74LS32、CD4511芯片,再加上數(shù)碼管、蜂鳴器、發(fā)光二極管、電阻這些器件組成一個(gè)簡單而靈敏的監(jiān)測報(bào)警電路,操作簡單,接通電源即可工作。因?yàn)榇蟛糠蛛娐凡捎脭?shù)字電路,所以本水位監(jiān)測報(bào)警器還具有耗能低、準(zhǔn)確性高的特點(diǎn)。關(guān)鍵字:譯碼電路    報(bào)警電路    監(jiān)測電路 Abstract: The water level alarm monitoring the use of 5 V low-voltage DC power (can also use three batteries replaced on the 5th) will be able to 5 to 15 centimeters of water level monitoring, with LED display and digital display of water level, and this can no longer Within the scope of a water level alarm. Mainly CD4066, 74LS86, 74LS32, CD4511 chips, coupled with digital control, buzzer, light-emitting diode, the resistance of these devices composed of a simple and Sensitive monitoring alarm circuits. Because the majority of circuits using digital circuitry, so the water level monitored alarm system also has low energy consumption, high accuracy of the characteristics. Keyword: Decoding circuit alarm circuit monitoring circuit

    標(biāo)簽: 水位 監(jiān)測報(bào)警 系統(tǒng)原理

    上傳時(shí)間: 2013-11-05

    上傳用戶:王慶才

  • 使用Artix-7 FPGA 降低您的系統(tǒng)功耗與成本

    As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-power,cost-Sensitive markets. Application classes like

    標(biāo)簽: Artix FPGA 功耗

    上傳時(shí)間: 2013-11-10

    上傳用戶:XLHrest

  • FPGA設(shè)計(jì)重利用方法(Design Reuse Methodology)

      FPGAs have changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost Sensitive designs. FPGAs had also been too expensive and tooslow for many applications, let alone for System Level Integration (SLI). Plus, the development

    標(biāo)簽: Methodology Design Reuse FPGA

    上傳時(shí)間: 2013-10-23

    上傳用戶:旗魚旗魚

  • 使用Artix-7 FPGA 降低您的系統(tǒng)功耗與成本

    As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-power,cost-Sensitive markets. Application classes like

    標(biāo)簽: Artix FPGA 功耗

    上傳時(shí)間: 2013-11-08

    上傳用戶:immanuel2006

  • FPGA設(shè)計(jì)重利用方法(Design Reuse Methodology)

      FPGAs have changed dramatically since Xilinx first introduced them just 15 years ago. In thepast, FPGA were primarily used for prototyping and lower volume applications; custom ASICswere used for high volume, cost Sensitive designs. FPGAs had also been too expensive and tooslow for many applications, let alone for System Level Integration (SLI). Plus, the development

    標(biāo)簽: Methodology Design Reuse FPGA

    上傳時(shí)間: 2013-11-01

    上傳用戶:shawvi

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