Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
標(biāo)簽：
design
hardware
includes
Encoder
上傳時(shí)間：
2013-12-15
上傳用戶(hù)：王者A
