Xilinx ISE Design SUITE是利用新技術(shù)來(lái)降低總設(shè)計(jì)成本的電子設(shè)計(jì)套件軟件，并且實(shí)現(xiàn)了比任何其它 PLD 解決方案更高的性能。
上傳時(shí)間： 2013-06-15
上傳用戶：eeworm
MicroC/OS-II The Real-Time Kernel Second Edition By Jean J. Labrosse CMP Books, CMP Media LLC Copyright 2002 by CMP Books ISBN 1-57820-103-9 CMP Books CMP Media LLC 1601 West 23rd Street, SUITE 200 Lawrence, Kansas 66046 785-841-1631 www.cmpbooks.com email: books@cmp.com The programs and applications on this disk have been carefully tested, but are not guaranteed for any particular purpose. The publisher does not offer any warranties and does not guarantee the accuracy, adequacy, or completeness of any information and is not responsible for any errors or omissions or the results obtained from use of such information.
標(biāo)簽： MicroCOS_II 嵌入式 實(shí)時(shí)操作系統(tǒng)
上傳時(shí)間： 2013-06-09
上傳用戶：zhyiroy
ADS（ARM Developer SUITE），是在1993年由Metrowerks公司開發(fā)是ARM處理器下最主要的開發(fā)工具。ADS 是全套的實(shí)時(shí)開發(fā)軟件工具，包編譯器生成的代碼密度和執(zhí)行速度優(yōu)異。可快速低價(jià)地創(chuàng)建ARM 結(jié)構(gòu)應(yīng)用。
上傳時(shí)間： 2013-07-20
上傳用戶：shenlan
ARM ADS全稱為ARM Developer SUITE。是ARM公司推出的新一代ARM集成開發(fā)工具。現(xiàn)在ADS的最新版本是1.2，它取代了早期的ADS1.1和ADS1.0。它除了可以安裝在Windows NT4，Windows 2000，Windows 98和Windows 95操作系統(tǒng)下，還支持Windows XP和Windows Me操作系統(tǒng)。 ADS由命令行開發(fā)工具，ARM時(shí)實(shí)庫(kù)，GUI開發(fā)環(huán)境(Code Warrior和AXD)，實(shí)用程序和支持軟件組成。 有了這些部件，用戶就可以為ARM系列的
上傳時(shí)間： 2013-04-24
上傳用戶：zhaiye
RealView Developer SUITE工具是ARM公司是推出的新一代ARM集成開發(fā)工具。支持所有ARM 系列核，并與眾多第三方實(shí)時(shí)操作系統(tǒng)及工具商合作簡(jiǎn)化開發(fā)流程。開發(fā)工具包含以下組件： ? 完全優(yōu)化的ISO C/C++編譯器 ? C++ 標(biāo)準(zhǔn)模板庫(kù) ? 強(qiáng)大的宏編譯器 ? 支持代碼和數(shù)據(jù)復(fù)雜存儲(chǔ)器布局的連接器 ? 可選 GUI調(diào)試器 ? 基于命令行的符號(hào)調(diào)試器(armsd) ? 指令集仿真器 ? 生成無(wú)格式二進(jìn)制工具、Intel 32位和Motorola 32位ROM映像代碼
上傳時(shí)間： 2013-08-02
上傳用戶：夢(mèng)不覺(jué)、
ispLEVER2.0是一套完整的EDA軟件。設(shè)計(jì)輸入可采用原理圖、硬件描述語(yǔ)言、混合輸入三種方式。能對(duì)所設(shè)計(jì)的數(shù)字電子系統(tǒng)進(jìn)行功能仿真和時(shí)序仿真。編譯器是此軟件的核心，能進(jìn)行邏輯優(yōu)化，將邏輯映射到器件中去，自動(dòng)完成布局與布線并生成編程所需要的熔絲圖件。軟件支持原有Lattice公司的GAL、ispLSI、MACH、ispGDX、ORCA2、ORCA3、ORCA4和最新的ispMACH器件。Xilinx.ISE.Design.SUITE（北京市電子設(shè)計(jì)競(jìng)賽指定軟件）
標(biāo)簽： ispLEVER2
上傳時(shí)間： 2013-04-24
上傳用戶：weddps
The LPC1700 Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous SUITE of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with Scatter-Gather DMA off-loads many operations from the CPU.
標(biāo)簽： 1700 MIIM LPC 以太網(wǎng)
上傳時(shí)間： 2013-11-09
上傳用戶：geshaowei
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design SUITE, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
The CodeWarrior Development SUITE provides access and technical support to amultitude of CodeWarrior products. In this quick start guide, Section 1 explains howto register your CodeWarrior Development SUITE. Section 2 explains how to activateand install one of your products. Section 3 describes what you are entitled to withthe purchase of your CodeWarrior Development SUITE, and Section 4 discusses theavailable purchase options. Section 5 describes the benefits of maintaining a currenttechnical support contract, and Section 6 tells you how to access support.
標(biāo)簽： CodeWarrior 開發(fā)套件
上傳時(shí)間： 2014-03-02
上傳用戶：784533221
This is the Xilinx Dual Processor Reference Designs SUITE. The designs illustrate a few differentdual-core architectures based on the MicroBlaze™ and PowerPC™ processors. The designsillustrate various concepts described in the Xilinx White Paper WP262 titled, “DesigningMultiprocessor Systems in Platform Studio”. There are simple software applications includedwith the reference designs that show various forms of interaction between the two processors.
標(biāo)簽： XAPP 996 雙處理器 參考設(shè)計(jì)
上傳時(shí)間： 2013-10-29
上傳用戶：旭521
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