基于scilab軟件的gmsk信號的調制
上傳時間： 2013-12-04
上傳用戶：lanhuaying
使用Scilab編寫的粒子群算法，例子比較簡單，無混沌搜索
上傳時間： 2017-06-15
上傳用戶：lnnn30
基于Scilab的粒子群算法代碼，Scilab是一個功能和matlab差不多的開源軟件
上傳時間： 2017-09-14
上傳用戶：小寶愛考拉
科學計算自由軟件SCILAB基礎教程，使用講解
上傳時間： 2021-10-10
上傳用戶：lanxin_eeworm
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
小波分解源代碼，基于Scilab！Scilab是一個OpenSource的類似matlab的工具，通過該源代碼可以為開發小波分析提供參考！
上傳時間： 2015-09-25
上傳用戶：王小奇
RTOS-嵌入式系統微內核概念和實現 Realtime Operating Systems Concepts and Implementation of Microkernels for Embedded Systems Dr. Jürgen Sauermann, Melanie Thelen
標簽： Implementation Microkernels Operating Concepts
上傳時間： 2014-01-03
上傳用戶：zgu489
BP人工神經網絡算法，用java代碼實現，用scilab圖像顯示，案例是港口吞吐量的預測
上傳時間： 2016-10-28
上傳用戶：思琦琦
Graphic Library for screen pg12864 handled by lpc21xx controller. Project was developed with IAR embedded workbench.
標簽： controller developed Graphic Library
上傳時間： 2017-04-23
上傳用戶：duoshen1989
