RADIX排序法
上傳時(shí)間: 2013-12-09
上傳用戶:hzy5825468
Merge, Insertion, RADIX, Heap, Bucket, Quick, Counting排序算法
標(biāo)簽: Insertion Counting Bucket Merge
上傳時(shí)間: 2014-01-09
上傳用戶:luke5347
GENERIC PROGRAM FOR A FAST LOOPED-CODE RADIX-2 DIT FFT
標(biāo)簽: LOOPED-CODE GENERIC PROGRAM RADIX
上傳時(shí)間: 2014-12-20
上傳用戶:zhangliming420
目錄: 0、 約定 1、 無符號(hào)數(shù)一位乘法 2、 符號(hào)數(shù)一位乘法 3、 布思算法(Booth algorithm) 4、 高基(High RADIX)布思算法 5、 迭代算法 6、 乘法運(yùn)算的實(shí)現(xiàn)——迭代 7、 乘法運(yùn)算的實(shí)現(xiàn)——陣列 8、 乘加運(yùn)算 9、 設(shè)計(jì)示例1 —— 8位、迭代 1、 實(shí)現(xiàn)方案1 —— 一位、無符號(hào) 2、 實(shí)現(xiàn)方案2 —— 一位、布思 3、 實(shí)現(xiàn)方案3 —— 二位 10、設(shè)計(jì)示例2 —— 16位、陣列 11、設(shè)計(jì)示例3 —— 32位、 迭代、陣列 1、 實(shí)現(xiàn)方案1 —— 乘、加一步走 2、 實(shí)現(xiàn)方案2 —— 乘、加兩步走
標(biāo)簽: algorithm Booth RADIX High
上傳時(shí)間: 2015-08-23
上傳用戶:qiaoyue
此程式具有三種FFT演算法,分別是RADIX-2 RADIX-4 RADIX-8,可選擇其中一種演算法,接著輸入FFT點(diǎn)數(shù),程式就會(huì)執(zhí)行FFT/IFFT,可以藉此知道是否正確
上傳時(shí)間: 2014-08-12
上傳用戶:84425894
54x54-bit RADIX-4 Multiplier based on Modified Booth Algorithm
標(biāo)簽: Multiplier Algorithm Modified RADIX
上傳時(shí)間: 2016-10-28
上傳用戶:李夢(mèng)晗
ADSP-TS101S and ADSP-TS201S Real and Complex RADIX-2 C-callable FFT
標(biāo)簽: ADSP-TS C-callable and Complex
上傳時(shí)間: 2016-11-28
上傳用戶:lizhen9880
verilog code RADIX-2 SRT divider input [7:0]Dividend input [3:0]Divisor output [4:0]Quotient output [8:0]Remainder
標(biāo)簽: input Dividend Quotient verilog
上傳時(shí)間: 2014-11-27
上傳用戶:三人用菜
RADIX-2 Fast Fourier Transform, real or complex sin/cos transform
標(biāo)簽: Transform transform Fourier complex
上傳時(shí)間: 2013-12-30
上傳用戶:rocketrevenge
This paper shows the development of a 1024-point RADIX-4 FFT VHDL core for applications in hardware signal processing, targeting low-cost FPGA technologies. The developed core is targeted into a Xilinx廬 Spartan鈩?3 XC3S200 FPGA with the inclusion of a VGA display interface and an external 16-bit data acquisition system for performance evaluation purposes. Several tests were performed in order to verify FFT core functionality, besides the time performance analysis highlights the core advantages over commercially available DSPs and Pentium-based PCs. The core is compared with similar third party IP cores targeting resourceful FPGA technologies. The novelty of this work is to provide a lowcost, resource efficient core for spectrum analysis applications.
標(biāo)簽: applications development hardware paper
上傳時(shí)間: 2013-12-21
上傳用戶:jichenxi0730
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