This set of files show some of the principles of Monte Carlo simulations, applied in the financila industry. this si the content of the web seminar called "Simulations de Monte Carlo en MATLAB".
標(biāo)簽： simulations principles financila the
上傳時(shí)間： 2013-12-18
上傳用戶：xiaoyunyun
ECE345, Visual-to-Audio Electronic Travel Aid Code for TM320C54x (v2a.asm) download This project involves the design and implementation of a audio synthesis device that converts moving images into audio signals. The system is built on a TM320C54x DSP with interface to an IMAQ camera module via the serial port on a PC. Brief description: A LabVIEW VI acquires an image from the IMAQ camera module. It quantizes the image into a 5x5, 3-bit image, and sends the data to the TM320C54x DSP via a serial port. The TM320C54x DSP constructs a 64-tap FIR by combining a series of 64-tap head related transfer functions (HRTF) according to the incoming data, and then filters an input audio signal with this FIR filter, in effect creating a correspondence between the filtered signal and the original image.
標(biāo)簽： Visual-to-Audio Electronic download project
上傳時(shí)間： 2017-02-01
上傳用戶：笨小孩
BP算法神經(jīng)網(wǎng)絡(luò)，是用C++寫的。功能強(qiáng)大。 有技術(shù)含量的。-BP neural network algorithm, is written in C. Powerful. A technical content
標(biāo)簽： BP算法 神經(jīng)網(wǎng)絡(luò)
上傳時(shí)間： 2017-02-17
上傳用戶：黃華強(qiáng)
介紹計(jì)算機(jī)上實(shí)現(xiàn)gsm modem短消息收發(fā)的模式，描述gsm modem PDU 模式，包括PDU 模式下的gsm modem模塊UCS2 編碼、解碼原理，以及gsm modem發(fā)送與接收PDU 串的編制方式， VB 中的MSCOMM 控件，實(shí)現(xiàn)gsm modem短消息收發(fā)的核心內(nèi)容。-briefed on computer modem gsm SMS transceiver model, described GSM modem PDU models, including the PDU mode GSM modem module UCS2 encoding, decoding principle, and GSM modems send and receive PDU Series presentation, the VB MSCOMM Control and achieve short GSM modem news transceiver core content
標(biāo)簽： modem gsm 計(jì)算機(jī) 收發(fā)
上傳時(shí)間： 2017-03-10
上傳用戶：cxl274287265
Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation. As with the SPI found in MC68HC11 processors the core features programmable clock phase [CPHA] and clock polarity [CPOL]. The core features an 8bit wishbone interface. Very simple, very small.
標(biāo)簽： Peripheral Interface available Enhanced
上傳時(shí)間： 2014-12-06
上傳用戶：invtnewer
tms320lf2407a work with at45db161 "trace". buffer 8000 word copy from sram to at45. first page content: num save, to cyclewrite. function: read trace to sram, save trace to at45, read status, and something else
標(biāo)簽： buffer 2407a first trace
上傳時(shí)間： 2014-12-05
上傳用戶：牛津鞋
pHash is an implementation of various perceptual hashing algorithms. A perceptual hash is a fingerprint of an audio, video, or image file that is mathematically based on the audio or visual content contained within. Unlike cryptographic hash functions that rely on the avalanche effect of small changes in input leading to drastic changes in the output, perceptual hashes are "close" to one another if the inputs are visually or auditorily similar. As a result, perceptual hashes must also be robust enough to take into account transformations that could have been performed on the input.
標(biāo)簽： perceptual implementation algorithms fingerpr
上傳時(shí)間： 2013-12-08
上傳用戶：星仔
簡(jiǎn)易聊天程序使用ajax+數(shù)據(jù)庫(kù)的實(shí)現(xiàn)，需要一個(gè)簡(jiǎn)單表字段name,content
標(biāo)簽： ajax 程序 數(shù)據(jù)庫(kù)
上傳時(shí)間： 2014-01-06
上傳用戶：Altman
USBHostSlave is a USB 1.1 host and Device IP core. – Supports full speed (12Mbps) and low speed (1.5Mbps) operation. – USB Device has four endpoints, each with their own independent FIFO. – Supports the four types of USB data transfer control, bulk, interrupt, and isochronous transfers. – Host can automatically generate SOF packets. – 8-bit Wishbone slave bus interface. – FIFO depth configurable via paramters.
標(biāo)簽： speed USBHostSlave and Supports
上傳時(shí)間： 2014-01-17
上傳用戶：sxdtlqqjl
This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
標(biāo)簽： Tensilica OpenCores interface the
上傳時(shí)間： 2013-12-21
上傳用戶：gonuiln
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