ADC0809是帶有8位A/D轉(zhuǎn)換器、8路多路開關以及微處理機兼容的控制邏輯的CMOS組件。它是逐次逼近式A/D轉(zhuǎn)換器,可以和單片機直接接口。 adc0809 datasheet
標簽: 0809 ADC 轉(zhuǎn)換器 應用技術
上傳時間: 2013-10-11
上傳用戶:kz_zank
介紹用PIC16C73 自帶的八位A/D 轉(zhuǎn)換器擴展為十二位A/D 轉(zhuǎn)換器,給出了具體的設計方案和程序流程。它是用以 PIC16C73 為MCU 構(gòu)成的海水有機磷測控儀A/D 轉(zhuǎn)換部分的一種解決方案。為監(jiān)測海洋生態(tài)環(huán)境,研制了用于海水有機磷農(nóng)藥現(xiàn)場監(jiān)測的生物傳感器。為測定生物傳感器的信號,使傳感器可用于船載及臺站的海洋生態(tài)環(huán)境現(xiàn)場自動監(jiān)測,需要對整個的采樣和排液裝置進行控制以及對傳感器來的信號進行實時采集處理,形成有機磷的濃度傳給上位機。為此,開發(fā)了以PIC16C73 單片機為核心的小型測控儀器,很好的完成了上述功能。PIC1673 單片機自帶8 位的A/D 轉(zhuǎn)換器,但不能滿足系統(tǒng)對精度的要求,本設計在單片機自帶8 位A/D 基礎上加少量的硬件和軟件開銷,使其擴展為十二位A/D 轉(zhuǎn)換器,滿足了系統(tǒng)的要求。
上傳時間: 2013-10-30
上傳用戶:a296386173
新穎實用的單片機雙積分A/D轉(zhuǎn)換電路和軟件:摘 要: 通過對雙積分A/ D 轉(zhuǎn)換過程及其原理的分析,結(jié)合8031 單片機定時計數(shù)器的特點,設計出一種新的A/ D 轉(zhuǎn)換電路. 詳細介紹了這種轉(zhuǎn)換電路的硬件原理及工作過程,給出了實用的硬件電路與軟件設計框圖. 通過比較分析,可以看出這種A/ D 轉(zhuǎn)換電路性能價格比較高,軟件編程簡單,并且轉(zhuǎn)換速度和精度優(yōu)于一般的A/ D 轉(zhuǎn)換電路. 這種設計思路為數(shù)模轉(zhuǎn)換器(A/ D) 的升級提高指出一個明確的方向.關鍵詞:單片機; 定時/ 計數(shù)器; A/ D 轉(zhuǎn)換; 雙積分 雙積分A/ D 及定時計數(shù)器原理:我們先分析雙積分A/ D 轉(zhuǎn)換的工作原理. 如圖1 所示,積分器先以固定時間T 對待測的輸入模擬電壓Vi 進行正向積分,積分電容C 積累的電荷為
標簽: 單片機 雙積分 轉(zhuǎn)換電路 軟件
上傳時間: 2014-01-18
上傳用戶:hewenzhi
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
標簽: synchronous Emulating serial
上傳時間: 2014-01-31
上傳用戶:z1191176801
18-2. D/A轉(zhuǎn)換器基本知識18-3. 光導智能小車硬件實現(xiàn)18-4. ADC0832基本應用方法18-5. 光導智能小車軟件實現(xiàn)A/D轉(zhuǎn)換器的主要技術指標分辨率 使輸出數(shù)字量變化一個相鄰數(shù)碼所需輸入模擬電壓的變化量。常 用二進制的位數(shù)表示。 例如:12位ADC的分辨率就是12位,一個10V滿刻度的12位ADC能分辨 輸入電壓變化最小是: 10V×1/212=2.4mV量化誤差 ADC把模擬量變?yōu)閿?shù)字量,用數(shù)字量近似表示模擬量,這個過程稱為量化。量化誤差是ADC的有限位數(shù)對模擬量進行量化而引起的誤差。A/D轉(zhuǎn)換器的主要技術指標偏移誤差 指輸入信號為零時,輸出信號不為零的值,所以有時又稱為零值誤差。滿刻度誤差 滿刻度誤差又稱為增益誤差。指滿刻度輸出數(shù)碼所對應的實際輸入電壓與理想輸入電壓之差。線性度 線性度有時又稱為非線性度,指轉(zhuǎn)換器實際的轉(zhuǎn)換特性與理想直線的最大偏差。A/D轉(zhuǎn)換器的主要技術指標絕對精度 在一個轉(zhuǎn)換器中,任何數(shù)碼所對應的實際模擬量輸入與理論模擬輸入之差的最大值,稱為絕對精度。對于ADC而言,可以在每一個階梯的水平中點進行測量,它包括了所有的誤差。轉(zhuǎn)換速率 指ADC能夠重復進行數(shù)據(jù)轉(zhuǎn)換的速度,即每秒轉(zhuǎn)換的次數(shù)。而完成一次A/D轉(zhuǎn)換所需的時間(包括穩(wěn)定時間),則是轉(zhuǎn)換速率的倒數(shù)。
上傳時間: 2013-11-25
上傳用戶:banlangen
Σ-ΔA/D技術具有高分辨率、高線性度和低成本的特點。本文基于TI公司的MSP430F1121單片機,介紹了采用內(nèi)置比較器和外圍電路構(gòu)成類似于Σ-△的高精度A/D實現(xiàn)方案,適合用于對溫度、壓力和電壓等緩慢變化信號的采集應用。 在各種A/D轉(zhuǎn)換器中,最常用是逐次逼近法(SAR)A/D,該類器件具有轉(zhuǎn)換時間固定且快速的特點,但難以顯著提高分辨率;積分型A/D 有較強的抗干擾能力,但轉(zhuǎn)換時間較長;過采樣Σ-ΔA/D由于其高分辨率,高線性度及低成本的特點,正得到越來越多的應用。根據(jù)這些特點,本文以TI公司的MSP430F1121單片機實現(xiàn)了一種類似于Σ-ΔA/D技術的高精度轉(zhuǎn)換器方案。 MSP430F1121是16位RISC結(jié)構(gòu)的FLASH型單片機,該芯片有14個雙向I/O口并兼有中斷功能,一個16位定時器兼有計數(shù)和定時功能。I/O口輸出高電平時電壓接近Vcc,低電平時接近Vss,因此,一個I/O口可以看作一位DAC,具有PWM功能。 該芯片具有一個內(nèi)置模擬電壓比較器,只須外接一只電阻和電容即可構(gòu)成一個類似于Σ-Δ技術的高精度單斜率A/D。一般而言,比較器在使用過程中會受到兩種因素的影響,一種是比較器輸入端的偏置電壓的積累;另一種是兩個輸入端電壓接近到一程度時,輸出端會產(chǎn)生振蕩。 MSP430F1121單片機在比較器兩輸入端對應的單片機端口與片外輸入信號的連接線路保持不變的情況下,可通過軟件將比較器兩輸入端與對應的單片機端口的連接線路交換,并同時將比較器的輸出極性變換,這樣抵消了比較器的輸入端累積的偏置電壓。通過在內(nèi)部將輸出連接到低通濾波器后,即使在比較器輸入端兩比較電壓非常接近,經(jīng)過濾波后也不會出現(xiàn)輸出端的振蕩現(xiàn)象,從而消除了輸出端震蕩的問題。利用內(nèi)置比較器實現(xiàn)高精度A/D圖1是一個可直接使用的A/D轉(zhuǎn)換方案,該方案是一個高精度的積分型A/D轉(zhuǎn)換器。其基本原理是用單一的I/O端口,執(zhí)行1位的數(shù)模轉(zhuǎn)換,以比較器的輸出作反饋,來維持Vout與Vin相等。圖1:利用MSP430F1121實現(xiàn)的實用A/D轉(zhuǎn)換器電路方案。
上傳時間: 2013-11-10
上傳用戶:lliuhhui
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
標簽: PicoBlaze Create Master Xilinx
上傳時間: 2013-11-05
上傳用戶:a6697238
AstroII-EVB-F1K(A)-L144開發(fā)板用戶指南
標簽: AstroII-EVB-F 144 開發(fā)板 用戶
上傳時間: 2013-11-22
上傳用戶:zhichenglu
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標簽: Base-Station Applications Single-Chip Transceiver
上傳時間: 2013-11-07
上傳用戶:songrui
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上傳時間: 2014-08-16
上傳用戶:adada