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Phase-lockedmloop

  • 基于CPLD的QDPSK調(diào)制解調(diào)電路設(shè)計

    為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式,在分析四相相對移相(QDPSK)信號調(diào)制解調(diào)原理的基礎(chǔ)上,設(shè)計了一種QDPSK調(diào)制解調(diào)電路,它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺上,進行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中,測試結(jié)果表明,調(diào)制電路能正確選相,解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致,達(dá)到了預(yù)期的設(shè)計要求。 Abstract:  In order to realize the better application of digital modulation mode QDPSK in the CDMA system, a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase,and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.

    標(biāo)簽: QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計

    上傳時間: 2013-10-28

    上傳用戶:jyycc

  • 基于Multisim 10的矩形波信號發(fā)生器仿真與實現(xiàn)

    在Multisim 10軟件環(huán)境下,設(shè)計一種由運算放大器構(gòu)成的精確可控矩形波信號發(fā)生器,結(jié)合系統(tǒng)電路原理圖重點闡述了各參數(shù)指標(biāo)的實現(xiàn)與測試方法。通過改變RC電路的電容充、放電路徑和時間常數(shù)實現(xiàn)了占空比和頻率的調(diào)節(jié),通過多路開關(guān)投入不同數(shù)值的電容實現(xiàn)了頻段的調(diào)節(jié),通過電壓取樣和同相放大電路實現(xiàn)了輸出電壓幅值的調(diào)節(jié)并提高了電路的帶負(fù)載能力,可作為頻率和幅值可調(diào)的方波信號發(fā)生器。Multisim 10仿真分析及應(yīng)用電路測試結(jié)果表明,電路性能指標(biāo)達(dá)到了設(shè)計要求。 Abstract:  Based on Multisim 10, this paper designed a kind of rectangular-wave signal generator which could be controlled exactly composed of operational amplifier, the key point was how to implement and test the parameter indicators based on the circuit diagram. The duty and the frequency were adjusted by changing the time constant and the way of charging and discharging of the capacitor, the width of frequency was adjusted by using different capacitors provided with multiple switch, the amplitude of output voltage was adjusted by sampling voltage and using in-phase amplifier circuit,the ability of driving loads was raised, the circuit can be used as squarewave signal generator whose frequency and amplitude can be adjusted. The final simulation results of Multisim 10 and the tests of applicable circuit show that the performance indicators of the circuit meets the design requirements.

    標(biāo)簽: Multisim 矩形波 信號發(fā)生器 仿真

    上傳時間: 2014-01-21

    上傳用戶:shen007yue

  • 簡單混合衰落信道 This mfile inputs an unmodulated sinewave through a simple Rayleigh two path fading channe

    簡單混合衰落信道 This mfile inputs an unmodulated sinewave through a simple Rayleigh two path fading channel and shows the output with phase, gain, and attenuation characteristics via animation.

    標(biāo)簽: unmodulated Rayleigh sinewave through

    上傳時間: 2015-05-17

    上傳用戶:CSUSheep

  • C++ Demystified: A Self-Teaching Guide by Jeff Kent ISBN:0072253703 McGraw-Hill/Osborne © 20

    C++ Demystified: A Self-Teaching Guide by Jeff Kent ISBN:0072253703 McGraw-Hill/Osborne © 2004 This hands-on, step-by-step resource will guide you through each phase of C++ programming, providing you with the foundation to discover how computer programs and programming languages work.

    標(biāo)簽: Self-Teaching Demystified McGraw-Hill 0072253703

    上傳時間: 2013-12-13

    上傳用戶:1427796291

  • The Hopfield model is a distributed model of an associative memory. Neurons are pixels and can take

    The Hopfield model is a distributed model of an associative memory. Neurons are pixels and can take the values of -1 (off) or +1 (on). The network has stored a certain number of pixel patterns. During a retrieval phase, the network is started with some initial configuration and the network dynamics evolves towards the stored pattern which is closest to the initial configuration.

    標(biāo)簽: model distributed associative Hopfield

    上傳時間: 2015-06-17

    上傳用戶:l254587896

  • The same two-stage decoder as above. However, when transforming the symbols prior to Viterbi decodin

    The same two-stage decoder as above. However, when transforming the symbols prior to Viterbi decoding, the amplitude information is ignored and only the phase of the received symbol is employed in the metric computation stage.

    標(biāo)簽: transforming two-stage However decoder

    上傳時間: 2015-07-05

    上傳用戶:sevenbestfei

  • This mfile illustrates a simple two path Rayleigh multipath fading channel This mfile inputs an unm

    This mfile illustrates a simple two path Rayleigh multipath fading channel This mfile inputs an unmodulated sinewave through a simple Rayleigh two path fading channel and shows the output with phase, gain, and attenuation characteristics via animation

    標(biāo)簽: mfile This illustrates multipath

    上傳時間: 2014-08-30

    上傳用戶:lindor

  • Blind Equalizer 的演算法主要是利用CMA及 LMS 的配合

    Blind Equalizer 的演算法主要是利用CMA及 LMS 的配合,當(dāng)CMA將EYE打開,使訊號趨近于正確值,就切換到LMS,利用Slicer的輸出當(dāng)作training sequence來調(diào)整Equalizer的系數(shù),而Carrier Recovery 的部份,則是將phase error track出來

    標(biāo)簽: Equalizer Blind CMA LMS

    上傳時間: 2013-12-28

    上傳用戶:it男一枚

  • 假近鄰法(False Nearest Neighbor, FNN)計算嵌入維的Matlab程序 文件夾說明: Main_FNN.m - 程序主函數(shù)

    假近鄰法(False Nearest Neighbor, FNN)計算嵌入維的Matlab程序 文件夾說明: Main_FNN.m - 程序主函數(shù),直接運行此文件即可 LorenzData.dll - 產(chǎn)生Lorenz時間序列 PhaSpaRecon.m - 相空間重構(gòu) fnn_luzhenbo.dll - 假近鄰計算主函數(shù) SearchNN.dll - 近鄰點搜索 buffer_SearchNN_1.dll - 近鄰點搜索緩存1 buffer_SearchNN_2.dll - 近鄰點搜索緩存2 參考文獻(xiàn): M.B.Kennel, R.Brown, H.D.I.Abarbanel. Determining embedding dimension for phase-space reconstruction using a geometrical construction[J]. Phys. Rev. A 1992,45:3403.

    標(biāo)簽: Main_FNN Neighbor Nearest Matlab

    上傳時間: 2013-12-10

    上傳用戶:songnanhua

  • 鎖相回路可視為一個輸出相位和輸入相位的回授系統(tǒng)用以同步輸入?yún)⒖加嵦柡突厥诤筝敵鲂盘枴2⒆屍洳僮魍瑯拥念l率。如(圖一)所示

    鎖相回路可視為一個輸出相位和輸入相位的回授系統(tǒng)用以同步輸入?yún)⒖加嵦柡突厥诤筝敵鲂盘枴2⒆屍洳僮魍瑯拥念l率。如(圖一)所示,簡單鎖相回路[3,4]是由三個電路構(gòu)成,分別為相位偵測器(Phase Detector)、回路濾波器(Loop Filter)、壓控蕩器(VCO)

    標(biāo)簽: 相位 輸入 鎖相回路 可視

    上傳時間: 2015-08-16

    上傳用戶:franktu

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