ORCAD在使用的時(shí)候總會(huì)出現(xiàn)這樣或那樣的問題…但下這個(gè)問題比較奇怪…在ORCAD中無法輸出網(wǎng)表…彈出下面的錯(cuò)誤….這種問題很是奇怪…Netlist Format: tango.dllDesign Name: D:\EDA_PROJECT\PROTEL99SE\YK\SV3200\MAIN.DSNERROR [NET0021] Cannot get Part.[FMT0024] Ref-des not found. Possible Logical/Physical annotation conflict.[FMT0018] Errors processing intermediate file找了一天沒找到問題…終于在花了N多時(shí)間后發(fā)現(xiàn)問題所在…其實(shí)這個(gè)問題就是不要使用ORCAD PSPICE 庫(kù)里面的元件來畫電路圖…實(shí)際中我是用了PSPICE里面和自己制作的二種電阻和電容混合在一起…就會(huì)出現(xiàn)這種問題…
上傳時(shí)間： 2013-11-21
上傳用戶：zaocan888
superpro 3000u 驅(qū)動(dòng) PIC16C65B@QFP44 [SA245] PIC16C65B: Part number QFP44: Package in QFP44 SA245: Adapter purchase number AM29DL320GT@FBGA48 [SA642+B026] AM29DL320GT: Part number FBGA48: Package in FBGA48 SA642: Adapter purchase number (Top board with socket) B026: Adapter purchase number (Bottom board, exchangable for different Parts) 87C196CA@PLCC68(universal adapter) [PEP+S414T] 87C196CA: Part number PLCC68: Package in PLCC68 universal adapter: this adapter is valid for all Parts in this package PEP: The PEP (Pin-driver Expansion Pack necessary to work with the adapter S414T) S414T: Adapter purchase number (Universal for all Parts in this package) S71PL127J80B@FBGA64(special adapter) [(SA642A-B079A-Y096AF001)] S71PL127J80B: Part number FBGA64: Package in FBGA64 special adapter: this adapter is valid for this
標(biāo)簽： superpro 3000u 驅(qū)動(dòng) 編程器軟件
上傳時(shí)間： 2013-10-23
上傳用戶：Avoid98
網(wǎng)上瘋傳的Excel BOM經(jīng)典腳本，相信諸位PADS用戶再熟悉不過了吧！ 但是它還有缺點(diǎn)： 1.元件封裝不能轉(zhuǎn)換。(元件位號(hào)為R/C/L的0402/063/0805/1206封裝自動(dòng)轉(zhuǎn)換統(tǒng)一的對(duì)應(yīng)封裝，以方便統(tǒng)計(jì)。) 2.元件參數(shù)轉(zhuǎn)換。(電阻的轉(zhuǎn)換0R時(shí)由0mR修正為0R,KR/MR修正為K/M。) 3.不能按元件的SMD屬性來分類統(tǒng)計(jì)。 4.有些公司在制作PADS庫(kù)元件時(shí)，已經(jīng)為元件建立了Part ID。導(dǎo)出BOM時(shí)需要元件的Part ID屬性。 5.不能導(dǎo)出元件坐標(biāo)。（本人改進(jìn)導(dǎo)出元件幾何中心坐標(biāo)，以便貼片生產(chǎn)之用。） 6.不能導(dǎo)出跳線。 7.不能支持WPS。 8.不能自定義導(dǎo)出元件的Part ID屬性。 9.不能自定義位號(hào)之間連接符號(hào)。 10.導(dǎo)出BOM特殊字符亂碼，比如常見的±/µ/Ω等。（PADS9.5在中文狀態(tài)下導(dǎo)出BOM就不會(huì)亂碼， 暫時(shí)還沒有更好的解決辦法，不過可以在Excel中替換解決。） 11.加載與運(yùn)行腳本步驟繁冗；運(yùn)行速度比較慢。（本人改進(jìn)的代碼速度絕對(duì)不會(huì)比之前的慢。）
上傳時(shí)間： 2015-01-01
上傳用戶：rolypoly152
通過以太網(wǎng)遠(yuǎn)程配置Nios II 處理器 應(yīng)用筆記 Firmware in embedded hardware systems is frequently updated over the Ethernet. For embedded systems that comprise a discrete microprocessor and the devices it controls, the firmware is the software image run by the microprocessor. When the embedded system includes an FPGA, firmware updates include updates of the hardware image on the FPGA. If the FPGA includes a Nios® II soft processor, you can upgrade both the Nios II processor—as Part of the FPGA image—and the software that the Nios II processor runs, in a single remote configuration session.
標(biāo)簽： Nios 遠(yuǎn)程 處理器 應(yīng)用筆記
上傳時(shí)間： 2013-11-22
上傳用戶：chaisz
Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,Part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上傳時(shí)間： 2013-10-12
上傳用戶：kang1923
This application note provides a detailed description of the SPartan™-3 configurationarchitecture. It explains the composition of the bitstream file and how this bitstream isinterpreted by the configuration logic to program the Part. Additionally, a methodology ispresented that will guide the user through the readback process. This information can be usedfor Partial reconfiguration or Partial readback.
標(biāo)簽： SPartan XAPP 452 架構(gòu)
上傳時(shí)間： 2013-11-16
上傳用戶：qingdou
This application note shows how to achieve low-cost, efficient serial configuration for SPartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, Part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing SPartan configuration.In Particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a SPartan design in the field by sending thebitstream over a network.
標(biāo)簽： SPartan XAPP FPGA 098
上傳時(shí)間： 2013-11-01
上傳用戶：wojiaohs
The standard that governs the design of avioniccomponents and systems, DO-254, is one of the mostpoorly understood but widely applicable standardsin the avionic industry. While information on thegeneral aspects of the standard is easy to obtain, thedetails of exactly how to implement the standard aresketchy. And once an entity develops a process thatachieves compliance, the details of how compliancewas achieved become Part of the intellectualproperty of that entity. This white paper focuses onthe details of developing a DO-254 compliantprocess for the design of FPGAs.
上傳時(shí)間： 2013-11-03
上傳用戶：ysystc670
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the Part is externally programmed?
標(biāo)簽： FPGA PLD 數(shù)據(jù)加密
上傳時(shí)間： 2013-10-20
上傳用戶：磊子226
Field Programmable Gate Arrays (FPGAs) are becoming a critical Part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.
上傳時(shí)間： 2013-10-22
上傳用戶：lmq0059
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