基于xilinx vierex5得pci express dma設(shè)計(jì)實(shí)現(xiàn)。
標(biāo)簽： vierex5 express xilinx pci
上傳時(shí)間： 2014-12-20
上傳用戶：chfanjiang
mini pci express datasheet
標(biāo)簽： datasheet express mini pci
上傳時(shí)間： 2013-11-25
上傳用戶：himbly
FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number generation and checking • ACK TLP packets • Scrambling • MemRd MemWr CfgRd CfgWr TLPs
標(biāo)簽： 8226 Testbench FEATURES training
上傳時(shí)間： 2014-01-18
上傳用戶：netwolf
PCI-express Lane Test Utility. Validates negotiated lane capability registers, returns error codes, supports multiple vendor/device ID s
標(biāo)簽： PCI-express negotiated capability Validates
上傳時(shí)間： 2013-12-21
上傳用戶：hwl453472107
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak performance of PCI Express is quite high, attaining that performance is a complex endeavor on top of an already complex protocol. The implementation is described and its performance is analyzed. Source code is offered for free download via the web.
標(biāo)簽： implementation describes mastering protocol
上傳時(shí)間： 2014-06-16
上傳用戶：teddysha
PCIE CEM規(guī)范：PCI Express CEM Revision 4.0
標(biāo)簽： pci express
上傳時(shí)間： 2021-11-30
上傳用戶：jiabin
在Cyclone IV GX收發(fā)器入門套件上,設(shè)計(jì)帶嵌入式收發(fā)器的Gen1×1硬核IP的 PCI Express IP編譯器。.rar
標(biāo)簽： 嵌入式
上傳時(shí)間： 2022-04-23
上傳用戶：kingwide
ANSI-VITA 46.4 PCI Express on the VPX ‘ANSI-VITA 46.4 PCI Express on the VPX’
標(biāo)簽： ANSI-VITA
上傳時(shí)間： 2022-06-26
上傳用戶：
PCI ExpressTM Architecture Add-in Card Compliance Checklist for the PCI Express Base 1.0a SpecificationThe PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.Contact the PCI Special Interest Group office to obtain the latest revision of this checklistQuestions regarding the ths document or membership in the PCI Special Interest Group may be forwarded tPCI Special Interest Group5440 SW Westgate Drive #217Portland, OR 97221Phone: 503-291-2569Fax: 503-297-1090 DISCLAIMERThis document is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
標(biāo)簽： Architecture ExpressTM PCI
上傳時(shí)間： 2013-11-03
上傳用戶：gy592333
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2013-10-15
上傳用戶：busterman
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