華為pcb布線規(guī)范
上傳時(shí)間： 2013-11-20
上傳用戶：han_zh
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2013-10-15
上傳用戶：busterman
隨著現(xiàn)代電子科技的發(fā)展, 大規(guī)模集成電路迅速普及，芯片逐漸向高速化和集成化方向發(fā)展, 其體積越來(lái)越小，頻率越來(lái)越高，電磁輻射隨其頻率的升高成平方倍增長(zhǎng)，使得各種電子設(shè)備系統(tǒng)內(nèi)外的電磁環(huán)境愈加復(fù)雜,對(duì)PCB 設(shè)計(jì)中的電磁兼容技術(shù)要求更高。PCB 電磁兼容設(shè)計(jì)是否合理直接影響設(shè)備的技術(shù)指標(biāo)，影響整個(gè)設(shè)備的抗干擾性能，直接關(guān)系到整個(gè)系統(tǒng)的可靠性和穩(wěn)定性。
標(biāo)簽： PCB 電磁輻射 實(shí)驗(yàn) 技術(shù)研究
上傳時(shí)間： 2013-11-09
上傳用戶：540750247
pcb檢查標(biāo)準(zhǔn)，即 pcb check list . 步驟非常之詳細(xì)，按著步驟一步一步的檢查就可以達(dá)到標(biāo)準(zhǔn)的。
標(biāo)簽： pcb 檢查標(biāo)準(zhǔn)
上傳時(shí)間： 2013-11-20
上傳用戶：my_cc
PCB布線對(duì)PCB的電磁兼容性影響很大，為了使PCB上的電路正常工作，應(yīng)根據(jù)本文所述的約束條件來(lái)優(yōu)化布線以及元器件/接頭和某些IC所用去耦電路的布局PCB材料的選擇通過(guò)合理選擇PCB的材料和印刷線路的布線路徑，可以做出對(duì)其它線路耦合低的傳輸線。當(dāng)傳輸線導(dǎo)體間的距離d小于同其它相鄰導(dǎo)體間的距離時(shí)，就能做到更低的耦合，或者更小的串?dāng)_（見(jiàn)《電子工程專輯》2000 年第1 期"應(yīng)用指南"）。設(shè)計(jì)之前，可根據(jù)下列條件選擇最經(jīng)濟(jì)的PCB形式：對(duì)EMC的要求·印制板的密集程度·組裝與生產(chǎn)的能力·CAD 系統(tǒng)能力·設(shè)計(jì)成本·PCB的數(shù)量·電磁屏蔽的成本當(dāng)采用非屏蔽外殼產(chǎn)品結(jié)構(gòu)時(shí)，尤其要注意產(chǎn)品的整體成本/元器件封裝/管腳樣式、PCB形式、電磁場(chǎng)屏蔽、構(gòu)造和組裝），在許多情況下，選好合適的PCB形式可以不必在塑膠外殼里加入金屬屏蔽盒。
標(biāo)簽： pcb 電磁兼容設(shè)計(jì)
上傳時(shí)間： 2013-11-01
上傳用戶：dddddd
PCB專業(yè)術(shù)語(yǔ)詞典
標(biāo)簽： pcb 術(shù)語(yǔ) 詞典
上傳時(shí)間： 2014-05-15
上傳用戶：頂?shù)弥?/p>
pcb Layout 設(shè)計(jì)從基礎(chǔ)到實(shí)踐多媒體教程
標(biāo)簽： Layout pcb 實(shí)踐 多媒體
上傳時(shí)間： 2013-11-19
上傳用戶：qw12
PCB板各個(gè)層的含義.pdf
標(biāo)簽： PCB
上傳時(shí)間： 2013-10-24
上傳用戶：yangzhiwei
PCB電子書刊12期.pdf
上傳時(shí)間： 2013-11-08
上傳用戶：小寶愛(ài)考拉
在Protel2004中進(jìn)行PCB的完備的CAM輸出。首先，我們可以輸出的gerber文件， 操作如下：1：畫好PCB后，在PCB 的文件環(huán)境中，左鍵點(diǎn)擊File\Fabrication Outputs\Gerber Files,進(jìn)入Gerber setup 界面
標(biāo)簽： Designer Altium CAM PCB
上傳時(shí)間： 2013-10-14
上傳用戶：aeiouetla
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