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  • HUAWEI ETS6630 3g無(wú)線固定臺(tái)產(chǎn)品用戶手冊(cè)-(V100R001_01,English,Normal).zip

    HUAWEI ETS6630 3g無(wú)線固定臺(tái)產(chǎn)品用戶手冊(cè)-(V100R001_01,English,Normal).zip

    標(biāo)簽: English HUAWEI Normal 6630

    上傳時(shí)間: 2017-02-25

    上傳用戶:h886166

  • software 15khz pal resolution new tool so you can see prgs on Normal tv

    software 15khz pal resolution new tool so you can see prgs on Normal tv

    標(biāo)簽: resolution software Normal prgs

    上傳時(shí)間: 2014-01-02

    上傳用戶:xiaodu1124

  • C++模擬Normal distribution

    C++模擬Normal distribution

    標(biāo)簽: distribution Normal

    上傳時(shí)間: 2013-12-25

    上傳用戶:PresidentHuang

  • generate a Normal sequence from rayleigh distribution

    generate a Normal sequence from rayleigh distribution

    標(biāo)簽: distribution generate sequence rayleigh

    上傳時(shí)間: 2017-07-02

    上傳用戶:www240697738

  • It is a software to decode information received by a Normal GPS like GARMIN, UBLOX if it sends NMEA

    It is a software to decode information received by a Normal GPS like GARMIN, UBLOX if it sends NMEA information

    標(biāo)簽: information software received GARMIN

    上傳時(shí)間: 2014-01-04

    上傳用戶:waitingfy

  • a real time counter component for delphi applications. You will notice that Normal timer function

    a real time counter component for delphi applications. You will notice that Normal timer functions in delphi is not enough for microseconds timing. This component let you get microseconds

    標(biāo)簽: applications component function counter

    上傳時(shí)間: 2017-09-17

    上傳用戶:zhangliming420

  • NE564的應(yīng)用電路描述

    The NE564 contains the functional blocks shown in Figure 1. Inaddition to the Normal PLL functio

    標(biāo)簽: 564 NE 應(yīng)用電路

    上傳時(shí)間: 2013-06-21

    上傳用戶:gxf2016

  • ADC轉(zhuǎn)換器技術(shù)用語(yǔ) (A/D Converter Defi

    ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the Normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.

    標(biāo)簽: Converter Defi ADC 轉(zhuǎn)換器

    上傳時(shí)間: 2013-11-12

    上傳用戶:pans0ul

  • Creating Safe State Machines(Mentor)

      Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its Normal operating condition.

    標(biāo)簽: Creating Machines Mentor State

    上傳時(shí)間: 2013-10-08

    上傳用戶:wangzhen1990

  • 模塊電源功能性參數(shù)指標(biāo)及測(cè)試方法

      模塊電源的電氣性能是通過(guò)一系列測(cè)試來(lái)呈現(xiàn)的,下列為一般的功能性測(cè)試項(xiàng)目,詳細(xì)說(shuō)明如下: 電源調(diào)整率(Line Regulation) 負(fù)載調(diào)整率(Load Regulation) 綜合調(diào)整率(Conmine Regulation) 輸出漣波及雜訊(Ripple & Noise) 輸入功率及效率(Input Power, Efficiency) 動(dòng)態(tài)負(fù)載或暫態(tài)負(fù)載(Dynamic or Transient Response) 起動(dòng)(Set-Up)及保持(Hold-Up)時(shí)間 常規(guī)功能(Functions)測(cè)試 1. 電源調(diào)整率   電源調(diào)整率的定義為電源供應(yīng)器于輸入電壓變化時(shí)提供其穩(wěn)定輸出電壓的能力。測(cè)試步驟如下:于待測(cè)電源供應(yīng)器以正常輸入電壓及負(fù)載狀況下熱機(jī)穩(wěn)定后,分別于低輸入電壓(Min),正常輸入電壓(Normal),及高輸入電壓(Max)下測(cè)量并記錄其輸出電壓值。 電源調(diào)整率通常以一正常之固定負(fù)載(Nominal Load)下,由輸入電壓變化所造成其輸出電壓偏差率(deviation)的百分比,如下列公式所示:   [Vo(max)-Vo(min)] / Vo(Normal) 2. 負(fù)載調(diào)整率   負(fù)載調(diào)整率的定義為開關(guān)電源于輸出負(fù)載電流變化時(shí),提供其穩(wěn)定輸出電壓的能力。測(cè)試步驟如下:于待測(cè)電源供應(yīng)器以正常輸入電壓及負(fù)載狀況下熱機(jī)穩(wěn)定后,測(cè)量正常負(fù)載下之輸出電壓值,再分別于輕載(Min)、重載(Max)負(fù)載下,測(cè)量并記錄其輸出電壓值(分別為Vo(max)與Vo(min)),負(fù)載調(diào)整率通常以正常之固定輸入電壓下,由負(fù)載電流變化所造成其輸出電壓偏差率的百分比,如下列公式所示:   [Vo(max)-Vo(min)] / Vo(Normal)    3. 綜合調(diào)整率   綜合調(diào)整率的定義為電源供應(yīng)器于輸入電壓與輸出負(fù)載電流變化時(shí),提供其穩(wěn)定輸出電壓的能力。這是電源調(diào)整率與負(fù)載調(diào)整率的綜合,此項(xiàng)測(cè)試系為上述電源調(diào)整率與負(fù)載調(diào)整率的綜合,可提供對(duì)電源供應(yīng)器于改變輸入電壓與負(fù)載狀況下更正確的性能驗(yàn)證。 綜合調(diào)整率用下列方式表示:于輸入電壓與輸出負(fù)載電流變化下,其輸出電壓之偏差量須于規(guī)定之上下限電壓范圍內(nèi)(即輸出電壓之上下限絕對(duì)值以內(nèi))或某一百分比界限內(nèi)。 4. 輸出雜訊   輸出雜訊(PARD)系指于輸入電壓與輸出負(fù)載電流均不變的情況下,其平均直流輸出電壓上的周期性與隨機(jī)性偏差量的電壓值。輸出雜訊是表示在經(jīng)過(guò)穩(wěn)壓及濾波后的直流輸出電壓上所有不需要的交流和噪聲部份(包含低頻之50/60Hz電源倍頻信號(hào)、高于20 KHz之高頻切換信號(hào)及其諧波,再與其它之隨機(jī)性信號(hào)所組成)),通常以mVp-p峰對(duì)峰值電壓為單位來(lái)表示。   一般的開關(guān)電源的規(guī)格均以輸出直流輸出電壓的1%以內(nèi)為輸出雜訊之規(guī)格,其頻寬為20Hz到20MHz。電源實(shí)際工作時(shí)最惡劣的狀況(如輸出負(fù)載電流最大、輸入電源電壓最低等),若電源供應(yīng)器在惡劣環(huán)境狀況下,其輸出直流電壓加上雜訊后之輸出瞬時(shí)電壓,仍能夠維持穩(wěn)定的輸出電壓不超過(guò)輸出高低電壓界限情形,否則將可能會(huì)導(dǎo)致電源電壓超過(guò)或低于邏輯電路(如TTL電路)之承受電源電壓而誤動(dòng)作,進(jìn)一步造成死機(jī)現(xiàn)象。   同時(shí)測(cè)量電路必須有良好的隔離處理及阻抗匹配,為避免導(dǎo)線上產(chǎn)生不必要的干擾、振鈴和駐波,一般都采用雙同軸電纜并以50Ω于其端點(diǎn)上,并使用差動(dòng)式量測(cè)方法(可避免地回路之雜訊電流),來(lái)獲得正確的測(cè)量結(jié)果。 5. 輸入功率與效率   電源供應(yīng)器的輸入功率之定義為以下之公式:   True Power = Pav(watt) = Vrms x Arms x Power Factor 即為對(duì)一周期內(nèi)其輸入電壓與電流乘積之積分值,需注意的是Watt≠VrmsArms而是Watt=VrmsArmsxP.F.,其中P.F.為功率因素(Power Factor),通常無(wú)功率因素校正電路電源供應(yīng)器的功率因素在0.6~0.7左右,其功率因素為1~0之間。   電源供應(yīng)器的效率之定義為為輸出直流功率之總和與輸入功率之比值。效率提供對(duì)電源供應(yīng)器正確工作的驗(yàn)證,若效率超過(guò)規(guī)定范圍,即表示設(shè)計(jì)或零件材料上有問(wèn)題,效率太低時(shí)會(huì)導(dǎo)致散熱增加而影響其使用壽命。 6. 動(dòng)態(tài)負(fù)載或暫態(tài)負(fù)載   一個(gè)定電壓輸出的電源,于設(shè)計(jì)中具備反饋控制回路,能夠?qū)⑵漭敵鲭妷哼B續(xù)不斷地維持穩(wěn)定的輸出電壓。由于實(shí)際上反饋控制回路有一定的頻寬,因此限制了電源供應(yīng)器對(duì)負(fù)載電流變化時(shí)的反應(yīng)。若控制回路輸入與輸出之相移于增益(Unity Gain)為1時(shí),超過(guò)180度,則電源供應(yīng)器之輸出便會(huì)呈現(xiàn)不穩(wěn)定、失控或振蕩之現(xiàn)象。實(shí)際上,電源供應(yīng)器工作時(shí)的負(fù)載電流也是動(dòng)態(tài)變化的,而不是始終維持不變(例如硬盤、軟驅(qū)、CPU或RAM動(dòng)作等),因此動(dòng)態(tài)負(fù)載測(cè)試對(duì)電源供應(yīng)器而言是極為重要的。可編程序電子負(fù)載可用來(lái)模擬電源供應(yīng)器實(shí)際工作時(shí)最惡劣的負(fù)載情況,如負(fù)載電流迅速上升、下降之斜率、周期等,若電源供應(yīng)器在惡劣負(fù)載狀況下,仍能夠維持穩(wěn)定的輸出電壓不產(chǎn)生過(guò)高激(Overshoot)或過(guò)低(Undershoot)情形,否則會(huì)導(dǎo)致電源之輸出電壓超過(guò)負(fù)載組件(如TTL電路其輸出瞬時(shí)電壓應(yīng)介于4.75V至5.25V之間,才不致引起TTL邏輯電路之誤動(dòng)作)之承受電源電壓而誤動(dòng)作,進(jìn)一步造成死機(jī)現(xiàn)象。 7. 啟動(dòng)時(shí)間與保持時(shí)間   啟動(dòng)時(shí)間為電源供應(yīng)器從輸入接上電源起到其輸出電壓上升到穩(wěn)壓范圍內(nèi)為止的時(shí)間,以一輸出為5V的電源供應(yīng)器為例,啟動(dòng)時(shí)間為從電源開機(jī)起到輸出電壓達(dá)到4.75V為止的時(shí)間。   保持時(shí)間為電源供應(yīng)器從輸入切斷電源起到其輸出電壓下降到穩(wěn)壓范圍外為止的時(shí)間,以一輸出為5V的電源供應(yīng)器為例,保持時(shí)間為從關(guān)機(jī)起到輸出電壓低于4.75V為止的時(shí)間,一般值為17ms或20ms以上,以避免電力公司供電中于少了半周或一周之狀況下而受影響。    8. 其它 在電源具備一些特定保護(hù)功能的前提下,還需要進(jìn)行保護(hù)功能測(cè)試,如過(guò)電壓保護(hù)(OVP)測(cè)試、短路保護(hù)測(cè)試、過(guò)功保護(hù)等

    標(biāo)簽: 模塊電源 參數(shù) 指標(biāo) 測(cè)試方法

    上傳時(shí)間: 2013-10-22

    上傳用戶:zouxinwang

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