This application NOTE shows how a Xilinx CoolRunnerTM-II CPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining CPLD resources
標簽： CoolRunner-II Xilinx XAPP CPLD
上傳時間： 2013-12-16
上傳用戶：qwer0574
Consumer display applications commonly use high-speed LVDS interfaces to transfer videodata. Spread-spectrum clocking can be used to address electromagnetic compatibility (EMC)issues within these consumer devices. This application NOTE uses Spartan®-6 FPGAs togenerate spread-spectrum clocks using the DCM_CLKGEN primitive.
上傳時間： 2013-11-01
上傳用戶：hjkhjk
This application NOTE covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-23
上傳用戶：shen_dafa
XAPP520將符合2.5V和3.3V I/O標準的7系列FPGA高性能I/O Bank進行連接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application NOTE describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上傳時間： 2013-11-06
上傳用戶：wentianyou
Xilinx is disclosing this user guide, manual, release NOTE, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
標簽： CPLD
上傳時間： 2014-12-05
上傳用戶：qazxsw
Hyperlynx仿真應用:阻抗匹配.下面以一個電路設計為例，簡單介紹一下PCB仿真軟件在設計中的使用。下面是一個DSP硬件電路部分元件位置關系(原理圖和PCB使用PROTEL99SE設計)，其中DRAM作為DSP的擴展Memory(64位寬度，低8bit還經過3245接到FLASH和其它芯片)，DRAM時鐘頻率133M。因為頻率較高，設計過程中我們需要考慮DRAM的數據、地址和控制線是否需加串阻。下面，我們以數據線D0仿真為例看是否需要加串阻。模型建立首先需要在元件公司網站下載各器件IBIS模型。然后打開Hyperlynx,新建LineSim File(線路仿真—主要用于PCB前仿真驗證)新建好的線路仿真文件里可以看到一些虛線勾出的傳輸線、芯片腳、始端串阻和上下拉終端匹配電阻等。下面，我們開始導入主芯片DSP的數據線D0腳模型。左鍵點芯片管腳處的標志，出現未知管腳，然后再按下圖的紅線所示線路選取芯片IBIS模型中的對應管腳。 3http://bbs.elecfans.com/ 電子技術論壇 http://www.elecfans.com 電子發燒友點OK后退到“ASSIGN Models”界面。選管腳為“Output”類型。這樣，一樣管腳的配置就完成了。同樣將DRAM的數據線對應管腳和3245的對應管腳IBIS模型加上(DSP輸出，3245高阻，DRAM輸入)。下面我們開始建立傳輸線模型。左鍵點DSP芯片腳相連的傳輸線，增添傳輸線，然后右鍵編輯屬性。因為我們使用四層板，在表層走線，所以要選用“Microstrip”，然后點“Value”進行屬性編輯。這里，我們要編輯一些PCB的屬性，布線長度、寬度和層間距等，屬性編輯界面如下：再將其它傳輸線也添加上。這就是沒有加阻抗匹配的仿真模型(PCB最遠直線間距1.4inch，對線長為1.7inch)。現在模型就建立好了。仿真及分析下面我們就要為各點加示波器探頭了，按照下圖紅線所示路徑為各測試點增加探頭：為發現更多的信息，我們使用眼圖觀察。因為時鐘是133M，數據單沿采樣，數據翻轉最高頻率為66.7M，對應位寬為7.58ns。所以設置參數如下：之后按照芯片手冊制作眼圖模板。因為我們最關心的是接收端(DRAM)信號，所以模板也按照DRAM芯片HY57V283220手冊的輸入需求設計。芯片手冊中要求輸入高電平VIH高于2.0V，輸入低電平VIL低于0.8V。DRAM芯片的一個NOTE里指出，芯片可以承受最高5.6V，最低-2.0V信號(不長于3ns)：按下邊紅線路徑配置眼圖模板：低8位數據線沒有串阻可以滿足設計要求，而其他的56位都是一對一，經過仿真沒有串阻也能通過。于是數據線不加串阻可以滿足設計要求，但有一點需注意，就是寫數據時因為存在回沖，DRAM接收高電平在位中間會回沖到2V。因此會導致電平判決裕量較小，抗干擾能力差一些，如果調試過程中發現寫RAM會出錯，還需要改版加串阻。
上傳時間： 2013-12-17
上傳用戶：debuchangshi
Abstract: This application NOTE presents an overview of electronic margining and its value in detectingpotential system failures before a product ships from the factory. It is a calibration method that effectivelypredicts and allows adjustments to improve product quality. Margining also can be used to sort productsinto performance levels, allowing premium products to be sold at premium prices. We discuss thedownside of sorting and suggest alternative ways to segregate products.
上傳時間： 2014-01-22
上傳用戶：lhw888
Abstract: This application NOTE discusses the REF pin functionality in the indirect current-feedbackarchitecture for instrumentation amplifiers. This article compares the importance of a REF buffer in a
上傳時間： 2015-01-03
上傳用戶：時代將軍
Abstract: Many modern industrial, medical, and commercial applications require temperature measurements in the extended temperature rangewith accuracies of ±0.3°C or better, performed with reasonable cost and often with low power consumption. This article explains how platinumresistance temperature detectors (PRTDs) can perform measurements over wide temperature ranges of -200°C to +850°C, with absolute accuracyand repeatability better than ±0.3°C, when used with modern processors capable of resolving nonlinear mathematical equation quickly and costeffectively. This article is the second installment of a series on PRTDs. For the first installment, please read application NOTE 4875, "High-Accuracy Temperature Measurements Call for Platinum Resistance Temperature Detectors (PRTDs) and Precision Delta-Sigma ADCs."
上傳時間： 2013-11-06
上傳用戶：WMC_geophy
Abstract: This application NOTE explains how to design an intelligent lighting controller that senses and measures the ambient lightlevel with an ambient light sensor (ALS). Equipped with a real-time clock (RTC), the controller also knows when to turn lighting on oroff at specified times. The system presented in this document can be used to control all luminaires that are mains-supply operated.Controller software is also provided in hex format.
上傳時間： 2013-11-18
上傳用戶：AbuGe
