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NIOS ii

  • 面向Eclips的NIOS ii軟件構(gòu)建工具手冊(cè)

    面向Eclips的NIOS ii軟件構(gòu)建工具手冊(cè) The Nios® II Software Build Tools (SBT) for Eclipse™ is a set of plugins based on the Eclipse™ framework and the Eclipse C/C++ development toolkit (CDT) plugins. The NIOS ii SBT for Eclipse provides a consistent development platform that works for all NIOS ii embedded processor systems. You can accomplish all NIOS ii software development tasks within Eclipse, including creating, editing, building, running, debugging, and profiling programs.

    標(biāo)簽: Eclips Nios 軟件

    上傳時(shí)間: 2013-11-02

    上傳用戶(hù):瓦力瓦力hong

  • 怎樣使用NIOS ii處理器來(lái)構(gòu)建多處理器系統(tǒng)

    怎樣使用NIOS ii處理器來(lái)構(gòu)建多處理器系統(tǒng) Chapter 1. Creating Multiprocessor NIOS ii Systems Introduction to NIOS ii Multiprocessor Systems . . . . . . . . . . . . . . 1–1 Benefits of Hierarchical Multiprocessor Systems  . . . . . . . . . . . . . . . 1–2 NIOS ii Multiprocessor Systems . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . . . . . 1–2 Multiprocessor Tutorial Prerequisites   . . . . . . . . . . .  . . . . . . . . . . . . 1–3 Hardware Designs for Peripheral Sharing   . . . . . . . . . . . .. . . . . . . . 1–3 Autonomous Multiprocessors   . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 1–3 Multiprocessors that Share Peripherals . . . . . . . . . . . . . . . . . . . . . . 1–4 Sharing Peripherals in a Multiprocessor System   . . . . . . . . . . . . . . . . . 1–4 Sharing Memory  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6 The Hardware Mutex Core  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 1–7 Sharing Peripherals   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . 1–8 Overlapping Address Space  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 1–8 Software Design Considerations for Multiple Processors . . .. . . . . 1–9 Program Memory  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–9 Boot Addresses  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1–13 Debugging NIOS ii Multiprocessor Designs  . . . . . . . . . . . . . . . .  1–15 Design Example: The Dining Philosophers’ Problem   . . . . .. . . 1–15 Hardware and Software Requirements . . . . . . . . . . . . . . . .. . . 1–16 Installation Notes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–17 Creating the Hardware System   . . . . . . . . . . . . . . .. . . . . . 1–17 Getting Started with the multiprocessor_tutorial_start Design Example   1–17 Viewing a Philosopher System   . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . 1–18 Philosopher System Pipeline Bridges  . . . . . . . . . . . . . . . . . . . . . 1–19 Adding Philosopher Subsystems   . . . . . . . . . . . . . . . . . . . . . .  . . . . 1–21 Connecting the Philosopher Subsystems  . . . . . . . . . . . . .. . . . . 1–22 Viewing the Complete System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–27 Generating and Compiling the System   . . . . . . . . . . . . . . . . . .. 1–28

    標(biāo)簽: Nios 處理器 多處理器

    上傳時(shí)間: 2013-11-21

    上傳用戶(hù):lo25643

  • 使用NIOS ii緊耦合存儲(chǔ)器教程

                 使用NIOS ii緊耦合存儲(chǔ)器教程 Chapter 1. Using Tightly Coupled Memory with the NIOS ii Processor Reasons for Using Tightly Coupled Memory  . . . . . . . . . . . . . . . . . . . . . . . 1–1 Tradeoffs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Guidelines for Using Tightly Coupled Memory . . . .. . . . . . . . 1–2 Hardware Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Software Guidelines  . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 1–3 Locating Functions in Tightly Coupled Memory  . . . . . . . . . . . . . 1–3 Tightly Coupled Memory Interface   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Restrictions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Dual Port Memories  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 1–5 Building a NIOS ii System with Tightly Coupled Memory  . . . . . . . . . . . 1–5

    標(biāo)簽: Nios 耦合 存儲(chǔ)器 教程

    上傳時(shí)間: 2013-10-13

    上傳用戶(hù):黃婷婷思密達(dá)

  • NIOS ii軟件開(kāi)發(fā)人員手冊(cè)中的緩存和緊耦合存儲(chǔ)器部分

            NIOS ii 軟件開(kāi)發(fā)人員手冊(cè)中的緩存和緊耦合存儲(chǔ)器部分 Nios® II embedded processor cores can contain instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the NIOS ii processor. Fortunately, most software based on the NIOS ii hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly. For code that needs direct control over the cache, the NIOS ii architecture provides facilities to perform the following actions:

    標(biāo)簽: Nios 軟件開(kāi)發(fā) 存儲(chǔ)器

    上傳時(shí)間: 2013-10-25

    上傳用戶(hù):蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)

  • NIOS ii定制指令用戶(hù)指南

         NIOS ii定制指令用戶(hù)指南:With the Altera NIOS ii embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the NIOS ii processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The NIOS ii configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the NIOS ii processor. The custom instruction logic connects directly to the NIOS ii arithmetic logic unit (ALU) as shown in Figure 1–1.

    標(biāo)簽: Nios 定制 指令 用戶(hù)

    上傳時(shí)間: 2013-10-12

    上傳用戶(hù):kang1923

  • NIOS ii 系列處理器配置選項(xiàng)

        NIOS ii 系列處理器配置選項(xiàng):This chapter describes the Nios® II Processor parameter editor in Qsys and SOPC Builder. The NIOS ii Processor parameter editor allows you to specify the processor features for a particular NIOS ii hardware system. This chapter covers the features of the NIOS ii processor that you can configure with the NIOS ii Processor parameter editor; it is not a user guide for creating complete NIOS ii processor systems.

    標(biāo)簽: Nios II 列處理器

    上傳時(shí)間: 2015-01-01

    上傳用戶(hù):mahone

  • NIOS ii內(nèi)核詳細(xì)實(shí)現(xiàn)

    NIOS ii內(nèi)核詳細(xì)實(shí)現(xiàn)

    標(biāo)簽: Nios 內(nèi)核

    上傳時(shí)間: 2015-01-01

    上傳用戶(hù):源碼3

  • NIOS ii是一個(gè)用戶(hù)可配置的通用RISC嵌入式處理器,這個(gè)文檔詳細(xì)介紹這個(gè)處理器的用法

    NIOS ii是一個(gè)用戶(hù)可配置的通用RISC嵌入式處理器,這個(gè)文檔詳細(xì)介紹這個(gè)處理器的用法

    標(biāo)簽: Nios RISC 用戶(hù) 可配置

    上傳時(shí)間: 2013-12-08

    上傳用戶(hù):ywqaxiwang

  • NIOS ii的uboot bootloader程序

    NIOS ii的uboot bootloader程序,完全可以在Nios SDK Shell下編譯。

    標(biāo)簽: bootloader uboot Nios 程序

    上傳時(shí)間: 2015-04-28

    上傳用戶(hù):一諾88

  • 這個(gè)是基于NIOS ii的FPGA平臺(tái)的一個(gè)CF卡的接口模塊

    這個(gè)是基于NIOS ii的FPGA平臺(tái)的一個(gè)CF卡的接口模塊,是在Quartus II下的完整工程包

    標(biāo)簽: NIOS FPGA 接口模塊

    上傳時(shí)間: 2015-05-04

    上傳用戶(hù):924484786

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