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Multiple-Output

  • 葉輪機械多級葉輪網格生成程序介紹 侯 樂 毅 非定常流課題組 本文開發的葉輪機械多級葉輪網格生成程序

    葉輪機械多級葉輪網格生成程序介紹 侯 樂 毅 非定常流課題組 本文開發的葉輪機械多級葉輪網格生成程序,采用的網格類型為H型,并在葉片前面/后面延伸區域設置平直網格數ID1和IDN。主程序MESH_BLADE_STAGES,分成三個部分,原始葉型及控制參數從輸入程序INPUT輸入,求解程序為GRID(ZERO),輸出程序為OUTPUT。

    標簽: 輪機 多級 網格 程序

    上傳時間: 2013-12-03

    上傳用戶:bjgaofei

  • This project demonstrates the use of secure hash functions technique to implement a file encryption

    This project demonstrates the use of secure hash functions technique to implement a file encryption / decryption system. This implemented application can encrypt / decrypt multiple files on the fly using a password. The password supplied by the user is used as the source message from which the hash code (key) is generated using the SHA algorithm. Then this key is used to enctypted the data in the file(s). This key is stored in the encrypted file along with the encrypted data.

    標簽: demonstrates encryption functions implement

    上傳時間: 2017-03-08

    上傳用戶:xuanchangri

  • This project demonstrates the use of secure hash functions technique to implement a file encryption

    This project demonstrates the use of secure hash functions technique to implement a file encryption / decryption system. This implemented application can encrypt / decrypt multiple files on the fly using a password. The password supplied by the user is used as the source message from which the hash code (key) is generated using the SHA algorithm. Then this key is used to enctypted the data in the file(s). This key is stored in the encrypted file along with the encrypted data.

    標簽: demonstrates encryption functions implement

    上傳時間: 2014-01-10

    上傳用戶:yyq123456789

  • This Telecommunication Standard [TS] describes the detailed mapping from input blocks of 160 speech

    This Telecommunication Standard [TS] describes the detailed mapping from input blocks of 160 speech samples in 13-bit uniform PCM format to encoded blocks of 95, 103, 118, 134, 148, 159, 204, and 244 bits and from encoded blocks of 95, 103, 118, 134, 148, 159, 204, and 244 bits to output blocks of 160 reconstructed speech samples

    標簽: Telecommunication describes Standard detailed

    上傳時間: 2013-12-12

    上傳用戶:cuibaigao

  • This is a source of 13.560MHz RFID card reader for TRH031M as ATMEGA8-16AU MPU. The title is 3Alogi

    This is a source of 13.560MHz RFID card reader for TRH031M as ATMEGA8-16AU MPU. The title is 3Alogics TRH031M 13.56MHz RFID Reader V1.0. project : RFID Reader V2.0 Target : MEGA8-16AU Crystal: 16.000 Mhz Input : TRH031M RFID 13.56MHz Output : RS232C 115200,N,8,1 Compiler : ICC-AVR V6.26C // Pin configuration for ATMEGA8-16AU TQFP32 // #30 RXD <--- RXD (SP3232) // #31 TXD ---> TXD (SP3232) // #32 PD2/INT0 <--- INTR (TRH031M) // # 1 PD3/INT1 ---> RST (TRH031M) // # 2 PD4 ---> D4 (TRH031M) // # 9 PD5 ---> D5 (TRH031M) // #10 PD6 ---> D6 (TRH031M) // #11 PD7 ---> D7 (TRH031M) // #12 PB0 ---> D0 (TRH031M) // #13 PB1 ---> D1 (TRH031M) // #14 PB2 ---> D2 (TRH031M) // #15 PB3 ---> D3 (TRH031M) // #16 PB4 ---> CSB (TRH031M) // #17 PB5 ---> LED // #23 PC0 ---> A0 (TRH031M) // #24 PC1 ---> A1 (TRH031M) // #25 PC2 ---> A2 (TRH031M) // #26 PC3 ---> ALE (TRH031M) // #27 PC4 ---> /RD (TRH031M) // #28 PC5 ---> /WR (TRH031M)

    標簽: 13.560 ATMEGA 3Alogi source

    上傳時間: 2017-03-31

    上傳用戶:s363994250

  • DESCRIPTION The DCP0105 family is a series of high efficiency, 5V input isolated DC/DC converters.

    DESCRIPTION The DCP0105 family is a series of high efficiency, 5V input isolated DC/DC converters. In addition to 1W nominal galvanically isolated output power capability, the range of DC/DCs are also fully synchronizable. The devices feature thermal shutdown, and overload protection is implemented via watchdog circuitry. Advanced power-on reset techniques give superior reset performance and the devices will start into any capacitive load up to full power output. The DCP0105 family is implemented in standard- molded IC packaging, giving outlines suitable for high volume assembly.

    標簽: DESCRIPTION efficiency converters isolated

    上傳時間: 2013-11-28

    上傳用戶:CHENKAI

  • The application note covers the various domains of the FIFO architecture, improving data rate using

    The application note covers the various domains of the FIFO architecture, improving data rate using the multiple buffering scheme, using the part in port I/O, slave FIFO or the GPIF

    標簽: architecture application improving the

    上傳時間: 2017-04-03

    上傳用戶:變形金剛

  • 使用FPGA/CPLD設置語音AD、DA轉換芯片AIC23

    使用FPGA/CPLD設置語音AD、DA轉換芯片AIC23,FPGA/CPLD系統時鐘為24.576MHz 1、AIC系統時鐘為12.288MHz,SPI時鐘為6.144MHz 2、AIC處于主控模式 3、input bit length 16bit output bit length 16bit MSB first 4、幀同步在96KHz

    標簽: FPGA CPLD AIC 23

    上傳時間: 2013-12-20

    上傳用戶:二驅蚊器

  • Shortest Paths with Multiplicative Cost. In a given undirected graph, the path cost is measured as a

    Shortest Paths with Multiplicative Cost. In a given undirected graph, the path cost is measured as a product of all the edges in the path. The weights are rational numbers (e.g., 0.25, 0.75, 3.75 etc) or integers (2, 3). There are no negative edges. Given such a graph as input, you are to output the shortest path between any two given vertices. Input is the adjacency matrix and the two vertices. You must output the path.

    標簽: Multiplicative undirected Shortest measured

    上傳時間: 2017-04-08

    上傳用戶:邶刖

  • In some graphs, the shortest path is given by optimizing two different metrics: the sum of weights o

    In some graphs, the shortest path is given by optimizing two different metrics: the sum of weights of the edges and the number of edges. For example: if two paths with equal cost exist then, the path with the least number of edges is chosen as the shortest path. Given this metric, you have find out the shortest path between a given pair of vertices in the input graph. The output should be the number of edges on the path, the cost of the shortest path, and the path itself. Input is the adjacency matrix and the two vertices.

    標簽: optimizing different the shortest

    上傳時間: 2014-10-25

    上傳用戶:1159797854

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