The CAT9534 is an 8-bit parallel input/output portexpander for I²C and SMBus compatible applications.These I/O expanders provide a simple solution inapplications where additional I/Os are needed: sensors,power switches, LEDs, pushbuttons, and fans.The CAT9534 consists of an input port register, anoutput port register, a configuration register, a polarityinversion register and an I²C/SMBus-compatible serialinterface.
上傳時間： 2013-11-09
上傳用戶：liulinshan2010
基于PIC單片機(jī)的脈沖電源:設(shè)計(jì)了一種金屬凝固過程用脈沖電源。該電源采用PIC16F877作為主控芯片，實(shí)現(xiàn)對窄脈沖電流幅值的檢測，以及時電流脈沖幅值根據(jù)模糊PID算法進(jìn)行閑環(huán)控制。使用結(jié)果表明：該電源的輸出脈沖波形良好，電流幅值穩(wěn)定，滿足合金材料凝固過程的工藝要求且運(yùn)行穩(wěn)定可靠。關(guān)鍵詞：脈沖電源；PIC16F877單片機(jī)；模糊PID；閑環(huán)控制 Abstract：A kind of pulse power supply was designed which uses in the metal solidification process ．．I11is power supply used PIC16F877 to take the master control chip reali on to the narrow pulse electric current peak-to-peak value examination，carried on the closed-loop control to the electric current pulse peak-to-peak value basis fuzzy PID algorithm．The use result indicated ，this power supply output se profile is good，and the electric current peak-to-p~k value is stable，It satisfies the alloy material solidification process the technological requirement and movement stable reliable，Key words：p se po wer supply；PIC16F877single-chip microcontroller；f r PID；closed-loop control
上傳時間： 2013-10-27
上傳用戶：xcy122677
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標(biāo)簽： Signal Input Fall Rise
上傳時間： 2013-10-23
上傳用戶：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上傳時間： 2014-04-02
上傳用戶：han_zh
有兩種方式可以讓設(shè)備和應(yīng)用程序之間聯(lián)系：1. 通過為設(shè)備創(chuàng)建的一個符號鏈；2. 通過輸出到一個接口WDM驅(qū)動程序建議使用輸出到一個接口而不推薦使用創(chuàng)建符號鏈的方法。這個接口保證PDO的安全，也保證安全地創(chuàng)建一個惟一的、獨(dú)立于語言的訪問設(shè)備的方法。一個應(yīng)用程序使用Win32APIs來調(diào)用設(shè)備。在某個Win32 APIs和設(shè)備對象的分發(fā)函數(shù)之間存在一個映射關(guān)系。獲得對設(shè)備對象訪問的第一步就是打開一個設(shè)備對象的句柄。 用符號鏈打開一個設(shè)備的句柄為了打開一個設(shè)備，應(yīng)用程序需要使用CreateFile。如果該設(shè)備有一個符號鏈出口，應(yīng)用程序可以用下面這個例子的形式打開句柄：hDevice = CreateFile("\\\\.\\OMNIPORT3", GENERIC_READ | GENERIC_WRITE,FILE_SHARE_READ, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL ,NULL);文件路徑名的前綴“\\.\”告訴系統(tǒng)本調(diào)用希望打開一個設(shè)備。這個設(shè)備必須有一個符號鏈，以便應(yīng)用程序能夠打開它。有關(guān)細(xì)節(jié)查看有關(guān)Kdevice和CreateLink的內(nèi)容。在上述調(diào)用中第一個參數(shù)中前綴后的部分就是這個符號鏈的名字。注意：CreatFile中的第一個參數(shù)不是Windows 98/2000中驅(qū)動程序(.sys文件)的路徑。是到設(shè)備對象的符號鏈。如果使用DriverWizard產(chǎn)生驅(qū)動程序，它通常使用類KunitizedName來構(gòu)成設(shè)備的符號鏈。這意味著符號鏈名有一個附加的數(shù)字，通常是0。例如：如果鏈接名稱的主干是L“TestDevice”那么在CreateFile中的串就該是“\\\\.\\TestDevice0”。如果應(yīng)用程序需要被覆蓋的I/O，第六個參數(shù)(Flags)必須或上FILE_FLAG_OVERLAPPED。 使用一個輸出接口打開句柄用這種方式打開一個句柄會稍微麻煩一些。DriverWorks庫提供兩個助手類來使獲得對該接口的訪問容易一些，這兩個類是CDeviceInterface, 和 CdeviceInterfaceClass。CdeviceInterfaceClass類封裝了一個設(shè)備信息集，該信息集包含了特殊類中的所有設(shè)備接口信息。應(yīng)用程序能有用CdeviceInterfaceClass類的一個實(shí)例來獲得一個或更多的CdeviceInterface類的實(shí)例。CdeviceInterface類是一個單一設(shè)備接口的抽象。它的成員函數(shù)DevicePath()返回一個路徑名的指針，該指針可以在CreateFile中使用來打開設(shè)備。下面用一個小例子來顯示這些類最基本的使用方法：extern GUID TestGuid;HANDLE OpenByInterface( GUID* pClassGuid, DWORD instance, PDWORD pError){ CDeviceInterfaceClass DevClass(pClassGuid, pError); if (*pError != ERROR_SUCCESS) return INVALID_HANDLE_VALUE; CDeviceInterface DevInterface(&DevClass, instance, pError); if (*pError != ERROR_SUCCESS) return INVALID_HANDLE_VALUE; cout << "The device path is " << DevInterface.DevicePath() << endl; HANDLE hDev; hDev = CreateFile( DevInterface.DevicePath(), GENERIC_READ | GENERIC_WRITE, FILE_SHARE_READ | FILE_SHARE_WRITE, NULL, OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL ); if (hDev == INVALID_HANDLE_VALUE) *pError = GetLastError(); return hDev;} 在設(shè)備中執(zhí)行I/O操作一旦應(yīng)用程序獲得一個有效的設(shè)備句柄，它就能使用Win32 APIs來產(chǎn)生到設(shè)備對象的IRPs。下面的表顯示了這種對應(yīng)關(guān)系。Win32 API DRIVER_FUNCTION_xxxIRP_MJ_xxx KDevice subclass member function CreateFile CREATE Create ReadFile READ Read WriteFile WRITE Write DeviceIoControl DEVICE_CONTROL DeviceControl CloseHandle CLOSECLEANUP CloseCleanUp 需要解釋一下設(shè)備類成員的Close和CleanUp：CreateFile使內(nèi)核為設(shè)備創(chuàng)建一個新的文件對象。這使得多個句柄可以映射同一個文件對象。當(dāng)這個文件對象的最后一個用戶級句柄被撤銷后，I/O管理器調(diào)用CleanUp。當(dāng)沒有任何用戶級和核心級的對文件對象的訪問的時候，I/O管理器調(diào)用Close。如果被打開的設(shè)備不支持指定的功能，則調(diào)用相應(yīng)的Win32將引起錯誤（無效功能）。以前為Windows95編寫的VxD的應(yīng)用程序代碼中可能會在打開設(shè)備的時候使用FILE_FLAG_DELETE_ON_CLOSE屬性。在Windows NT/2000中，建議不要使用這個屬性，因?yàn)樗鼘?dǎo)致沒有特權(quán)的用戶企圖打開這個設(shè)備，這是不可能成功的。I/O管理器將ReadFile和WriteFile的buff參數(shù)轉(zhuǎn)換成IRP域的方法依賴于設(shè)備對象的屬性。當(dāng)設(shè)備設(shè)置DO_DIRECT_IO標(biāo)志，I/O管理器將buff鎖住在存儲器中，并且創(chuàng)建了一個存儲在IRP中的MDL域。一個設(shè)備可以通過調(diào)用Kirp::Mdl來存取MDL。當(dāng)設(shè)備設(shè)置DO_BUFFERED_IO標(biāo)志，設(shè)備對象分別通過KIrp::BufferedReadDest或 KIrp::BufferedWriteSource為讀或?qū)懖僮鳙@得buff地址。當(dāng)設(shè)備不設(shè)置DO_BUFFERED_IO標(biāo)志也不設(shè)置DO_DIRECT_IO，內(nèi)核設(shè)置IRP 的UserBuffer域來對應(yīng)ReadFile或WriteFile中的buff參數(shù)。然而，存儲區(qū)并沒有被鎖住而且地址只對調(diào)用進(jìn)程有效。驅(qū)動程序可以使用KIrp::UserBuffer來存取IRP域。對于DeviceIoControl調(diào)用，buffer參數(shù)的轉(zhuǎn)換依賴于特殊的I/O控制代碼，它不在設(shè)備對象的特性中。宏CTL_CODE（在winioctl.h中定義）用來構(gòu)造控制代碼。這個宏的其中一個參數(shù)指明緩沖方法是METHOD_BUFFERED, METHOD_IN_DIRECT, METHOD_OUT_DIRECT, 或METHOD_NEITHER。下面的表顯示了這些方法和與之對應(yīng)的能獲得輸入緩沖與輸出緩沖的KIrp中的成員函數(shù)：Method Input Buffer Parameter Output Buffer Parameter METHOD_BUFFERED KIrp::IoctlBuffer KIrp::IoctlBuffer METHOD_IN_DIRECT KIrp::IoctlBuffer KIrp::Mdl METHOD_OUT_DIRECT KIrp::IoctlBuffer KIrp::Mdl METHOD_NEITHER KIrp::IoctlType3InputBuffer KIrp::UserBuffer 如果控制代碼指明METHOD_BUFFERED，系統(tǒng)分配一個單一的緩沖來作為輸入與輸出。驅(qū)動程序必須在向輸出緩沖放數(shù)據(jù)之前拷貝輸入數(shù)據(jù)。驅(qū)動程序通過調(diào)用KIrp::IoctlBuffer獲得緩沖地址。在完成時，I/O管理器從系統(tǒng)緩沖拷貝數(shù)據(jù)到提供給Ring 3級調(diào)用者使用的緩沖中。驅(qū)動程序必須在結(jié)束前存儲拷貝到IRP的Information成員中的數(shù)據(jù)個數(shù)。如果控制代碼不指明METHOD_IN_DIRECT或METHOD_OUT_DIRECT，則DeviceIoControl的參數(shù)呈現(xiàn)不同的含義。參數(shù)InputBuffer被拷貝到一個系統(tǒng)緩沖，這個緩沖驅(qū)動程序可以通過調(diào)用KIrp::IoctlBuffer。參數(shù)OutputBuffer被映射到KMemory對象，驅(qū)動程序?qū)@個對象的訪問通過調(diào)用KIrp::Mdl來實(shí)現(xiàn)。對于METHOD_OUT_DIRECT，調(diào)用者必須有對緩沖的寫訪問權(quán)限。注意，對METHOD_NEITHER，內(nèi)核只提供虛擬地址；它不會做映射來配置緩沖。虛擬地址只對調(diào)用進(jìn)程有效。這里是一個用METHOD_BUFFERED的例子：首先，使用宏CTL_CODE來定義一個IOCTL代碼：#define IOCTL_MYDEV_GET_FIRMWARE_REV \CTL_CODE (FILE_DEVICE_UNKNOWN,0,METHOD_BUFFERED,FILE_ANY_ACCESS)現(xiàn)在使用一個DeviceIoControl調(diào)用：BOOLEAN b;CHAR FirmwareRev[60];ULONG FirmwareRevSize;b = DeviceIoControl(hDevice, IOCTL_MYDEV_GET_VERSION_STRING, NULL, // no input 注意，這里放的是包含有執(zhí)行操作命令的字符串指針 0, FirmwareRev, //這里是output串指針，存放從驅(qū)動程序中返回的字符串。sizeof(FirmwareRev),& FirmwareRevSize, NULL // not overlapped I/O );如果輸出緩沖足夠大，設(shè)備拷貝串到里面并將拷貝的資結(jié)束設(shè)置到FirmwareRevSize中。在驅(qū)動程序中，代碼看起來如下所示：const char* FIRMWARE_REV = "FW 16.33 v5";NTSTATUS MyDevice::DeviceControl( KIrp I ){ ULONG fwLength=0; switch ( I.IoctlCode() ) { case IOCTL_MYDEV_GET_FIRMWARE_REV: fwLength = strlen(FIRMWARE_REV)+1; if (I.IoctlOutputBufferSize() >= fwLength) { strcpy((PCHAR)I.IoctlBuffer(),FIRMWARE_REV); I.Information() = fwLength; return I.Complete(STATUS_SUCCESS); } else { } case . . . } }
標(biāo)簽： 驅(qū)動程序 應(yīng)用程序 接口
上傳時間： 2013-10-17
上傳用戶：gai928943
The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog output, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.
上傳時間： 2013-10-22
上傳用戶：taiyang250072
為了擴(kuò)大監(jiān)控范圍，提高資源利用率，降低系統(tǒng)成本，提出了一種多通道視頻切換的解決方案。首先從視頻信號分離出行場信號，然后根據(jù)行場信號由DSP和FPGA產(chǎn)生控制信號，控制多路視頻通道之間的切換，從而實(shí)現(xiàn)讓一個視頻處理器同時監(jiān)控不同場景。實(shí)驗(yàn)結(jié)果表明，該方案可以在視頻監(jiān)控告警系統(tǒng)中穩(wěn)定、可靠地實(shí)現(xiàn)視頻通道的切換。 Abstract: To expand the scope of monitoring， improve resource utilization， reduce system cost， a multiple video channels signal switching method is pointed out in this paper. First， horizontal sync signal and field sync signal from the video signal are separated， then control signal according to the sync signal by DSP and FPGA is generated to control the switching between multiple video channels. Thus， it achieves to make a video processor to monitor different place. Experimental results show that the method can realize video channel switching reliably， and is applied in the video monitoring warning system successfully.
上傳時間： 2013-11-09
上傳用戶：不懂夜的黑
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時間： 2013-10-15
上傳用戶：euroford
針對嵌入式機(jī)器視覺系統(tǒng)向獨(dú)立化、智能化發(fā)展的要求，介紹了一種嵌入式視覺系統(tǒng)--智能相機(jī)。基于對智能相機(jī)體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析，對國內(nèi)外的幾款智能相機(jī)進(jìn)行比較。綜合技術(shù)發(fā)展現(xiàn)狀，提出基于FPGA+DSP模式的硬件平臺，并提出智能相機(jī)的發(fā)展方向。分析結(jié)果表明，該系統(tǒng)設(shè)計(jì)可以實(shí)現(xiàn)脫離PC運(yùn)行，完成圖像獲取與分析，并作出相應(yīng)輸出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision systems to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.
標(biāo)簽： FPGA DSP 模式 智能相機(jī)
上傳時間： 2013-10-24
上傳用戶：bvdragon
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對移相（QDPSK)信號調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計(jì)
上傳時間： 2014-01-13
上傳用戶：qoovoop
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