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the file contain many matlab signal source code and many example .
標(biāo)簽： many contain example matlab
上傳時間： 2014-01-20
上傳用戶：com1com2
he LPC932 can be used to create a Pulse Width Modulated PWM signal. That s an analog signal, with only 2 discrete levels, for example 0V and 5V and a constant period. The current value of this signal at a certain poiTnt of time is proportional to its Duty Cycle. That s the High Time during one period divided by the period. It can also be calculated as the average value during a particular period. That means after low pass filtering, (e.g. RC circuit) the signal becomes analog, with an actual value controlled by the microcontroller. The PWM functionality enables the LPC932 to control for example the speed of DC motors or the brightness of electric lighting.
標(biāo)簽： signal Modulated analog create
上傳時間： 2015-05-14
上傳用戶：CHINA526
Low-pass signal filtering by convolution
標(biāo)簽： convolution filtering Low-pass signal
上傳時間： 2013-12-16
上傳用戶：330402686
OFDM信號及其頻譜 OFDM signal and its spectrum ( Guard Interval insertion )
標(biāo)簽： OFDM insertion Interval spectrum
上傳時間： 2015-05-17
上傳用戶：wang5829
Real-time Digital Signal Processing with the TMS320C6000——DSP結(jié)構(gòu)的學(xué)習(xí)筆記。
標(biāo)簽： Processing Real-time Digital Signal
上傳時間： 2015-06-04
上傳用戶：270189020
BIOSIG is an open source software library for biomedical signal processing. Library works well with Octave and Matlab. Special emphasis is put on EEG/MEG/ECoG, but also other types of biosignals like ECG, EMG, etc. are supported.
標(biāo)簽： biomedical processing software Library
上傳時間： 2013-12-29
上傳用戶：ruan2570406
signal processing of lpc matlab done
標(biāo)簽： processing signal matlab done
上傳時間： 2015-06-09
上傳用戶：asasasas
speech signal process tools
標(biāo)簽： process speech signal tools
上傳時間： 2013-12-22
上傳用戶：123啊
matlab7@digital signal process enjoy!
標(biāo)簽： digital process matlab signal
上傳時間： 2015-07-01
上傳用戶：fandeshun
crack for ModelSim, a Verilog, VHDL and mixed VHDL / Verilog CAD simulator for FPGA, board and IC design.
標(biāo)簽： Verilog VHDL and for
上傳時間： 2015-07-10
上傳用戶：15736969615
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