The LTM8020, LTM8021, LTM8022 and LTM8023 μModule®regulators are complete easy-to-use encapsulated stepdownDC/DC regulators intended to take the pain and aggravationout of implementing a switching power supplyonto a system board. With a μModule regulator, you onlyneed an input cap, output cap and one or two resistorsto complete the design. As one might imagine, this highlevel of integration greatly simplifi es the task of printedcircuit board design, reducing the effort to four categories:component footprint generation, component placement,routing the nets, and thermal vias.
上傳時(shí)間： 2014-01-18
上傳用戶：laomv123
Analog Inputs and Outputs in an S7 PLC are represented in the PLC as a 16-bit integer. Over the nominal span of the analog input or output, the value of this integer will range between - 27648 and +27648. However, it is easier to use the analog values if they are scaled to the same units and ranges as the process being controlled. This applications tip describes methods for scaling analog values to and from engineering units.
上傳時(shí)間： 2013-11-17
上傳用戶：3294322651
The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed toenhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvementsinclude higher drive capability, 5 V I/O tolerance, lower supply current, individual I/Oconfiguration, and smaller packaging. I/O expanders provide a simple solution whenadditional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Outputand Polarity Inversion (active HIGH or active LOW operation) registers. The systemmaster can enable the I/Os as either inputs or outputs by writing to the I/O configurationbits. The data for each Input or Output is kept in the corresponding Input or Outputregister. The polarity of the read register can be inverted with the Polarity Inversionregister. All registers can be read by the system master. Although pin-to-pin and I2C-busaddress compatible with the PCF8575, software changes are required due to theenhancements, and are discussed in Application Note AN469.
上傳時(shí)間： 2013-11-13
上傳用戶：fredguo
The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption and a high-impedance open-drain output pin, IO0. The system master can enable the PCA9557’s I/O as either input or output by writing to the configuration register. The system master can also invert the PCA9557 inputs by writing to the active HIGH polarity inversion register. Finally, the system master can reset the PCA9557 in the event of a time-out by asserting a LOW in the reset input. The power-on reset puts the registers in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part.
標(biāo)簽： C-bus SMBus reset port
上傳時(shí)間： 2014-01-18
上傳用戶：bs2005
The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are orientedin the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic inputand output buffer separated by TI’s silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to4000 V. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, andprevent noise currents on a data bus or other circuits from entering the local ground and interfering with ordamaging sensitive circuitry.
標(biāo)簽： ISOLATORS DIGITAL DUAL
上傳時(shí)間： 2013-10-24
上傳用戶：hbsunhui
程序存儲(chǔ)問題:設(shè)有n 個(gè)程序{1,2,…, n }要存放在長度為L的磁帶上。程序i存放在磁帶上的長度是Li ，1≤i≤n 程序存儲(chǔ)問題要求確定這n 個(gè)程序在磁帶上的一個(gè)存儲(chǔ)方案，使得能夠在磁帶上存儲(chǔ)盡可能多的程序。 編程任務(wù)： 對于給定的n個(gè)程序存放在磁帶上的長度，編程計(jì)算磁帶上最多可以存儲(chǔ)的程序數(shù)。 數(shù)據(jù)輸入：由文件input.txt給出輸入數(shù)據(jù)。第一行是正整數(shù)n，表示文件個(gè)數(shù)。接下來的1 行中，有n 個(gè)正整數(shù)，表示程序存放在磁帶上的長度。 結(jié)果輸出: input.txt output.txt 6 50 5 2 3 13 8 80 20
上傳時(shí)間： 2013-12-20
上傳用戶：dongqiangqiang
This example program shows how to configure and use the A/D Converter of the following microcontroller: STMicroelectronics ST10F166 After configuring the A/D, the program reads the A/D result and outputs the converted value using the serial port. To run this program... Build the project (Project Menu, Build Target) Start the debugger (Debug Menu, Start/Stop Debug Session) View the Serial Window (View Menu, Serial Window #1) View the A/D converter peripheral (Peripheral Menu, A/D Converter) Run the program (Debug Menu, Go) A debug script (debug.ini) creates buttons that set different analog values in A/D channels. As the program runs, you will see the A/D input and output change. Other buttons create signals that generate sine wave or sawtooth patterns as analog inputs. µ Vision3 users may enable the built-in Logic Analyzer to view, measure and compare these input signals graphically.
標(biāo)簽： microcontroll Converter configure following
上傳時(shí)間： 2014-12-01
上傳用戶：獨(dú)孤求源
這是CISS會(huì)議上發(fā)表的著名論文“Tensor Canonical decomposition based method for blind identification of MIMO system with 3-input 2-output case”的源程序，主要是講基于張量規(guī)范分解的多天線系統(tǒng)的忙識(shí)別問題，里邊包含了相應(yīng)的文章，可以一起對照著看。
標(biāo)簽： identification decomposition Canonical Tensor
上傳時(shí)間： 2015-10-21
上傳用戶：牛津鞋
This simulation script set allows for an OFDM transmission to be simulated. Imagetx.m generates the OFDM signal, saving it as a windows WAV file. This allows the OFDM signal to be played out a sound card and recorded back. Imagerx.m decodes the WAV to extract the data. settings.m contains all the common settings to specify all the simulation parameters such as FFT size, number of carriers, input data source file, input and output WAV files, etc.
標(biāo)簽： transmission simulation generates simulated
上傳時(shí)間： 2013-12-15
上傳用戶：dyctj
An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.
標(biāo)簽： interconnections approach general include
上傳時(shí)間： 2015-12-12
上傳用戶：lyy1234
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