This is the Xilinx Dual Processor Reference Designs suite. The designs illustrate a few differentdual-core architectures based on the MICROBLAZE™ and PowerPC™ processors. The designsillustrate various concepts described in the Xilinx White Paper WP262 titled, “DesigningMultiprocessor Systems in Platform Studio”. There are simple software applications includedwith the reference designs that show various forms of interaction between the two processors.
標(biāo)簽： XAPP 996 雙處理器 參考設(shè)計(jì)
上傳時(shí)間： 2013-10-29
上傳用戶：旭521
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or MICROBLAZE™ microprocessor.
上傳時(shí)間： 2014-11-26
上傳用戶：erkuizhang
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MICROBLAZE™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
摘要：本文簡要介紹了Xilinx最新的EDK9.1i和ISE9.1i等工具的設(shè)計(jì)使用流程，最終在采用65nm工藝級(jí)別的Xilinx Virtex-5 開發(fā)板ML505 上同時(shí)設(shè)計(jì)實(shí)現(xiàn)了支持TCP/IP 協(xié)議的10M/100M/1000M 的三態(tài)以太網(wǎng)和千兆光以太網(wǎng)的SOPC 系統(tǒng),并對(duì)涉及的關(guān)鍵技術(shù)進(jìn)行了說明。關(guān)鍵詞：FPGA；EDK；SOPC；嵌入式開發(fā)；EMAC；MICROBLAZE 本研究采用業(yè)界最新的Xilinx 65ns工藝級(jí)別的Virtex-5LXT FPGA 高級(jí)開發(fā)平臺(tái)，滿足了對(duì)于建造具有更高性能、更高密度、更低功耗和更低成本的可編程片上系統(tǒng)的需求。Virtex-5以太網(wǎng)媒體接入控制器(EMAC)模塊提供了專用的以太網(wǎng)功能，它和10/100/1000Base-T外部物理層芯片或RocketIOGTP收發(fā)器、SelectIO技術(shù)相結(jié)合，能夠分別實(shí)現(xiàn)10M/100M/1000M的三態(tài)以太網(wǎng)和千兆光以太網(wǎng)的SOPC 系統(tǒng)。
標(biāo)簽： FPGA 千兆以太網(wǎng)
上傳時(shí)間： 2013-10-28
上傳用戶：DE2542
uC/OS-II Notes from Nohau Corporation The code associated with this readme.txt file is provided "as is". The code was written with the intention of creating a functional RTOS demo for the Nohau evaluation boards that can run a MICROBLAZE core. You can use this code for any and all of your projects, as you see fit. Nohau Corporation does not warrant that the code is bug-free, and will provide no support for this RTOS port.
標(biāo)簽： Corporation associated provided readme
上傳時(shí)間： 2013-12-27
上傳用戶：tzl1975
Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not MICROBLAZE.
標(biāo)簽： Spartan drives This perphrials
上傳時(shí)間： 2014-05-29
上傳用戶：SimonQQ
本程序用xilinx EDK9.1運(yùn)行，通過MICROBLAZE軟核，實(shí)現(xiàn)在sparton——3e板卡上的按鍵及開關(guān)的控制，通過RS－232與超級(jí)終端進(jìn)行通信。
上傳時(shí)間： 2016-10-02
上傳用戶：qiao8960
賽靈思的FPGA，設(shè)計(jì)的軟核MICROBLAZE示例
上傳時(shí)間： 2017-03-13
上傳用戶：libinxny
原創(chuàng)作品，真正可用的超小型 bootloader。將存于norflash里的elf文件裝入ram運(yùn)行，比xilinx提供的bootloader好用多了，至少可以節(jié)省你1周的時(shí)間. 嵌入式系統(tǒng)用 edk powerpc 或 MICROBLAZE 通用
標(biāo)簽：
上傳時(shí)間： 2017-07-10
上傳用戶：a6697238
EGO1 是依元素科技基于 Xilinx Artix-7 FPGA 研發(fā)的便攜式數(shù)模混合基礎(chǔ)教 學(xué)平臺(tái)。EGO1 配備的 FPGA (XC7A35T-1CSG324C)具有大容量高性能等特點(diǎn)， 能實(shí)現(xiàn)較復(fù)雜的數(shù)字邏輯設(shè)計(jì)；在 FPGA 內(nèi)可以構(gòu)建 MICROBLAZE 處理器系統(tǒng)， 可進(jìn)行 SoC 設(shè)計(jì)。該平臺(tái)擁有豐富的外設(shè)，以及靈活的通用擴(kuò)展接口。
上傳時(shí)間： 2017-10-14
上傳用戶：wlwl
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