The MSP-FET430PIF is a Parallel Port interface (does not include target board) that is used to program and debug MSP430 FET tools and test boards through the JTAG interface. This interface is included in our FET tools, but sold without the development board. This interface uses a Parallel PC Port to communicate to the Debugger Software (IAR Kickstart software included) running on the PC. The interface uses the standard 14 pin header to communicate to the MSP430 device using the standard JTAG protocol. The flash memory can be erased and programmed in seconds with only a few keystrokes, and since the MSP430 flash is extremely low power, no external power supply is required. The tool has an integrated software environment and connects directly to the PC which greatly simplifies the set-up and use of the tool. The flash development tool supports development with all MSP430 flash parts. Features MSP430 debugging interface to connect a MSP430-Flash-device to a Parallel port on a PC Supports JTAG debug protocol (NO support for Spy-Bi-Wire (2-wire JTAG) debug protocol, Spy-Bi-Wire (2-wire JTAG) is supported by MSP-FET430UIF) Parallel Port cable and a 14-conductor target cable Full documentation on CD ROM Integrated IAR Kickstart user interface which includes: Assembler Linker Limulator Source-level debugger Limited C-compiler Technical specifications: Backwardly compatable with existing FET tool boards.
上傳時間： 2013-10-26
上傳用戶：fengweihao158@163.com
Although Stellaris microcontrollers have generous internal SRAM capabilities, certain applicationsmay have data storage requirements that exceed the 8 KB limit of the Stellaris LM3S8xx seriesdevices. Since microcontrollers do not have an external parallel data-bus, serial memory optionsmust be considered. Until recently, the ubiquitous serial EEPROM/flash device was the only serialmemory solution. The major limitations of EEPROM and flash technology are slow write speed, slowerase times, and limited write/erase endurance.Recently, serial SRAM devices have become available as a solution for high-speed dataapplications. The N256S08xxHDA series of devices, from AMI Semiconductor, offer 32 K x 8 bits oflow-power data storage, a fast Serial Peripheral Interface (SPI) serial bus, and unlimited write cycles.The parts are available in 8-pin SOIC and compact TSSOP packages.
上傳時間： 2013-10-14
上傳用戶：cxl274287265
基于單DSP的VoIP模擬電話適配器研究與實現:提出和實現了一種新穎的基于單個通用數字信號處理器(DSP)的VoIP模擬電話適配器方案。DSP的I/O和存儲資源非常有限，通常適于運算密集型應用，不適宜控制密集型應用[5]。該系統高效利用單DSP的I/O和片內外存儲器資源，采用μC/OS-II嵌入式實時操作系統，支持SIP和TCP-UDP/IP協議，通過LAN或者寬帶接入，使普通電話機成為Internet終端，實現IP電話。該系統軟硬件結構緊湊高效，運行穩定，成本低，具有廣闊的應用前景。關鍵詞：模擬電話適配器；IP電話；數字信號處理器；μC/OS-II 【Abstract】This paper presents a VoIP ATA solution based on a single digital signal processor (DSP). DSPs are suitable for arithmetic-intensiveapplication and unsuitable for control-intensive application because of the limitation of I/O and memory resources. This solution is based on a 16-bitfixed-point DSP and μC/OS-II embedded real-time operating system. It makes good use of the limited resources, supports SIP and TCP-UDP/IPprotocol. It can connect the analog telephone to Internet and realize the VoIP application. This system has a great future for its high efficiency andlow cost.【Key words】Analog telephone adapter (ATA); Voice over Internet protocol (VoIP); Digital signal processor (DSP); μC/OS-II Research and Implementation of VoIPATA Based on Single DSP
上傳時間： 2013-11-20
上傳用戶：Wwill
In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
上傳時間： 2013-10-08
上傳用戶：18711024007
介紹一種人機交互系統的可靠性設計方案。該系統基于Memory-link通信協議，采用了目前流行的基于ARM7架構的S3C44BOX作為主控芯片，通過RS-422實現人機交互通信。結合抗干擾的硬件設計和穩定有效運行的軟件設計方案，實現了在強干擾下穩定可靠的通信。實驗結果表明，本系統抗干擾能力強、運行穩定可靠，在自主開發控制系統的人機交互通信部分具有一定的參考價值。
標簽： Memory-link 協議 人機交互系統 可靠性設計
上傳時間： 2013-11-21
上傳用戶：cknck
Hopfield Model Autoassociative Memory 源碼, 經典的HOPFIELD人工神經網絡例子源碼
標簽： Autoassociative Hopfield HOPFIELD Memory
上傳時間： 2015-01-05
上傳用戶：皇族傳媒
Bidirectional Associative Memory Heteroassociative Memory 人工智能人工神經網絡源碼;
標簽： Memory Heteroassociative Bidirectional Associative
上傳時間： 2015-01-05
上傳用戶：372825274
提供字符串、文件 及 Memory Streams 加密/解密的控件 ( 2.1 版，附原始程序代碼 )，作者 : Konstantin Borodachev。
上傳時間： 2013-12-28
上傳用戶：stvnash
This book introduces embedded systems to C and C++ programmers. Topics include testing memory devices, writing and erasing Flash memory, verifying nonvolatile memory contents, controlling on-chip peripherals, device driver design and implementation, optimizing embedded code for size and speed, and making the most of C++ without a performance penalty. Pages : 336 Slots : 1
標簽： programmers introduces embedded include
上傳時間： 2013-12-10
上傳用戶：shizhanincc
memory management
標簽： management memory
上傳時間： 2015-01-12
上傳用戶：凌云御清風
