Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
標簽： representation Magnitude the magnitude
上傳時間： 2013-12-24
上傳用戶：金宜
CFlowchartEditor is an extension of CDiagramEditor. CDiagramEditor is a vector editor, with a CWnd-derived window (CDiagramEditor), a data container (CDiagramEntityContainer) holding the draw-objects, undo stack and managing copy and paste, and objects derived from CDiagramEntity representing objects drawn on screen. CDiagramEditor lacks one feature (that is difficult to implement in both simple and general fashion) - links. Manually maintaining links in a - for example - flowchart or network topography map is unwieldy. Therefore, I ve created a reference implementation for one way of adding this functionality.
標簽： CDiagramEditor CFlowchartEditor extension CWnd-d
上傳時間： 2015-11-21
上傳用戶：氣溫達上千萬的
First of all, the Applet-phone is a SIP User-Agent with audio and text messaging capabilities. But i s also embedded in an applet where you can use it as usual if your firewall allow you to use the UDP transport. If not, you can use TCP to carry your voice in a voice messaging fashion. Your voice is recorded and encoded locally then sent as a message, decoded and played back by your peer. Voice messaging allow you to go through any firewall, so that you can continue to chat and talk with your friends from an applet !
標簽： Applet-phone capabilities User-Agent messaging
上傳時間： 2014-01-11
上傳用戶：c12228
Cypress Semiconductor makes a variety of PLL-based clock generators. This application note provides a set of recommendations to optimize usage of Cypress clock devices in a system. The application note begins with recommended termination techniques for clock generators. Subsequently, power supply filtering and bypassing is discussed. Finally, the application note provides some recommendations on board layout.
標簽： Semiconductor application generators PLL-based
上傳時間： 2013-12-20
上傳用戶：水中浮云
In this talk we will consider two approaches in dealing with the risk of supplier bankruptcy. In the first model, we study the effects of supply disruption risk in a supply chain where one buyer deals with competing risky suppliers who may default during their production lead-times.
標簽： approaches bankruptcy the consider
上傳時間： 2014-08-04
上傳用戶：lanjisu111
Yet another Java implementation for the addictive Minesweeper game. This game comes with a number of options unavailable in Windows s version, such as allowing more than one mines in a square.
標簽： game implementation Minesweeper addictive
上傳時間： 2014-01-06
上傳用戶：zhaiyanzhong
An AHB system is made of masters slaves and interconnections. A general approach to include all possible "muxed" implementation of multi layered AHB systems and arbitrated AHB ones can be thought as an acyclic graph where every source node is a master, every destination node is a slave and every internal node is an arbiter there must be one and only one arc exiting a master and one or more entering a slave (single slave verus multi-slave or arbitrated slave) an arbiter can have as many input and output connections as needed. A bridge is a special node that collapses one or more slave nodes and a master node in a new "complex" node.
標簽： interconnections approach general include
上傳時間： 2015-12-12
上傳用戶：lyy1234
this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.
標簽： implementation include quartus source
上傳時間： 2013-12-25
上傳用戶：壞壞的華仔
This package consists of the executable (UCW), a default script file, this file, and the library files. It is important that the header files end up in a include subdirectory of the directory where UCW is found. If you unzip this file using its path information ( use folder names ) this will automatically happen. You can optionally specify the UnderC directory with the environment variable UC_HOME note that this points to the directory containing ucw.exe. If you do this, then you can copy the executable anywhere and it will still be able to find the header files.
標簽： file executable the consists
上傳時間： 2013-12-17
上傳用戶：asddsd
Welcome to UnderC version 1.2.9w This package consists of the executable (UCW), a default script file, this file, and the library files. It is important that the header files end up in a include subdirectory of the directory where UCW is found. If you unzip this file using its path information ( use folder names ) this will automatically happen. You can optionally specify the UnderC directory with the environment variable UC_HOME note that this points to the directory containing ucw.exe. If you do this, then you can copy the executable anywhere and it will still be able to find the header files.
標簽： executable consists Welcome package
上傳時間： 2015-12-18
上傳用戶：baiom
